Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors on a single chip at each technology generation. On the other hand, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the number of transient faults in circuits tends to increase. Moreover, energy reduction techniques also negatively affect the reliability of circuits. Traditional high-level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. Especially the effect of using different voltage levels on reliability is completely ignored by previous studies. In this article, we present two new HLS methods for application-specific integrated circuit (ASIC) design under area and timing constraints with the objectives of low energy consumption and high reliability. For the mapping and scheduling steps of HLS, we propose integer linear programming (ILP) and genetic algorithm (GA)-based optimization methods. While ILP provides the optimum results, the CPU time increases exponentially with the number of application nodes. On the other hand, GA-based metaheuristic is faster and determines optimum or near-optimum results in shorter times than ILP. Additionally, we use a selective duplication method to further improve the overall reliability.

Multiprocessor task scheduling is one of the hardest combinatorial optimization problems in parallel and distributed systems. It is known as NP-hard and therefore, scanning the whole search space using an exact algorithm to find the optimal solution is not practical. Instead, metaheuristics are mostly employed to find a near-optimal solution in a reasonable amount of time. In this paper, a multi-population based parallel genetic algorithm is presented for the optimization of multiprocessor task scheduling in the presence of communication costs. To the best of our knowledge, this parallel genetic algorithm approach is applied to the problem at hand for the first time using a benchmark set that includes well-known task graphs from different sources. Our experiments conducted on several task graphs with different sizes from the benchmark set showed the superiority of the approach over a conventional genetic algorithm and the related works in the literature in terms of two different performance metrics. Our parallel implementation not only decreased the execution time but also increased the quality of the scheduling solutions considerably.

With the migration to deep sub-micron process technologies, the power consumption of a circuit has come to the forefront of concerns, and as a result, the power has become a critical design parameter. This paper presents a novel high-level synthesis methodology, called Power Islands Synthesis, that eliminates the spurious switching activity and the leakage in a great portion of the resulting circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independently from the rest of the circuit and hence can be completely powered down when all of the logic it contains is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. By powering down an island during its idle cycles, the following occur: 1) The spurious switching that results from the broadcast to idle components is silenced and 2) the power consumption due to leakage in inactive components is eliminated. Experiments conducted on several synthesis benchmarks implemented at the layout level with a 65-nm process technology and simulated using a transistor-level simulator showed power savings ranging from 5% to 20% due to our methodology. The reported savings were entirely from the power down of combinational elements (functional resources) of the data path.

A large fraction of the total power dissipated in a digital circuit is consumed by the clocked elements in the data-path. Hence, savings in power usage of these components can be directly reflected in a circuit's overall power consumption. Reducing power through techniques that optimize power consumption in combinational elements has been extensively discussed in the existing literature. However, these techniques cannot be applied for reducing the power in sequential elements. In this work, we focus on this problem, and introduce a novel cluster-based register optimization technique that is employed in High-Level Synthesis (HLS) with Power Islands. Our experiments conducted on several synthesis benchmarks implemented at the transistor level using a 65 nm process technology showed anaverage reduction of 18% in total power consumption due to our technique with no or little area overhead.