In a 3D TLC solid-state storage system, the LDPC decoding performance is significantly affected by the quality of soft-level sensing. Inspired by the capacity-approaching maximum mutual-information method, this work presents the data-driven approach to collect all the optimal 2-bit soft-read level pairs over the 3D TLC NAND. Due to the data transmission latency and limited configuration resources, a clustering method is proposed to extract the soft-read level pairs in the experiment data. Under the 3K Program Erase Cycles 228-hour data retention at 85°C channel condition, the proposed soft-read level pairs could provide an additional 73-error-bit tolerance in the 2K LDPC decoder.

This paper presents a reconfigurable LDPC decoder implementation fully compliant with all the configurations in the 5G NR standard. Based on the row-based layered normalized Min-Sum (NMS) algorithm, the optimization approaches are proposed to solve the data dependency hazard in the pipeline process. The proposed instruction-level reordering diminishes the redundant latency of our pipelined decoder architecture. Moreover, the proposed data-level rescheduling optimizes the decoding sequence to remove the remaining pipeline stalls in the high- throughput design without decoding performance degradation. Evaluated in Xilinx VCU1525 FPGA, our design achieves a throughput of 6.7 Gbps per iteration. Implemented in TSMC 28nm CMOS process at the post-layout stage, a 33.2 Gbps, in one iteration, throughput can be achieved at a clock rate 556 MHz with the core area 1.97 mm2.

EDA tools are necessary to assist complicated flow of advanced IC design and verification in nowadays industry. After synthesis or simulation, the same signal could be viewed as different hierarchical names, especially for mixed-language designs. This name mismatching problem blocks automation and needs experienced users to rectify manually with domain knowledge. Even rule-based rectification helps the process but still fails when encountering unseen mismatching types. In this paper, hierarchical name rectification is transformed into the similarity search problem where the most similar name becomes the rectified name. However, naive full search in design with string comparison costs unacceptable time. Our proposed framework embeds name strings into vectors for representing distance relation in a latent space using character n-gram and locality-sensitive hashing (LSH), and then finds the most similar signal using nearest neighbor search (NNS) and detailed search. Learning similarity using Siamese network provides general name rectification regardless of mismatching types, while string-to-vector embedding for proximity search accelerates the recti-fication process. Our approach is capable of achieving 93.43% rectification rate with only 0.052s per signal, which outperforms the naive string search with 2.3% higher accuracy and 4,500 times speed-up.

The SM4 algorithm is the first commercial cipher published by China in 2012 which is widely used in WLAN WAPI resource restricted devices. This paper proposed the single-round-iterative architecture which can operate at 500 MHZ clock frequency and reach 2Gbps throughput. In order to resist side channel attack, we changed the S-box structure and add secret sharing during the computation process. According to the CPA result, this hardware is secure under the condition of collecting 1 million power traces. The gate count of this design is about 15.19k, gaining almost 17.7% area reduction to the BMTSM4 which can reach the similar throughput [1].

Decoding high code rate Turbo codes by their reciprocal dual trellis has been shown to be potentially beneficial in implementation due to the simpler trellis structures. However, reciprocal dual trellis decoders' complexity grows significantly when the code rate is less than 1/2. Further, designing a multi-code rate reciprocal dual trellis decoder is even more challenging if periodical puncturing patterns is not always available. In this paper, a radix-4 hybrid-trellis LTE-A turbo decoder with a controller switching between the conventional trellis and the reciprocal dual trellis is presented. To accommodate all the rates defined in LTE-A, a zero patching scheme is proposed to create the periodical puncturing patterns required by the reciprocal dual trellis decoding. The implementation of the proposed decoder supports all the code rates, from 1/3 to 0.95, and all the 188 block lengths. Fabricated in TSMC TN28HPM process, the post-layout simulations show the proposed decoder could achieve 333Mbps at 6 iterations under 263MHz operating frequency. The core area is 1.08 mm2, and the decoder draws 295.57 mW of power with energy efficiency of 0.148(nJ/bit/iter).

In this paper, two globally-coupled low-density parity check (GC-LDPC) code constructing methods are presented. The first is a Reed-Solomon-like GC-LDPC code that eases the design parameter searching in algebraic code constructions. The parameters such as the finite field, the associated prime factors, or the number of local codes can be more easily determined. The directly masking approach, the second proposed scheme, facilitates flexible structure designs of the parity check matrices. The two approaches can be regarded as generalizations of the original GC-LDPC codes. The design examples and the simulation results show the feasibility of the proposed techniques. In addition to code constructions, some applications and usage scenarios of GC-LDPC codes are addressed as well.

Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down design methodology, which not only goes through code construction and optimization, but also hardware implementation to meet all the critical requirements, is presented. A two-step array dispersion algorithm is proposed to construct long LDPC codes with a small submatrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain better bit-error rate (BER) performance and lower error-floor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix leading to a proposed hybrid storage architecture, which has the advantages of better area efficiency and large enough data bandwidth for high decoding throughput. To be adopted for NAND flash applications, an (18900, 17010) LDPC code with a code-rate of 0.9 and submatrix size of 63 is constructed and the field-programmable gate array simulations show that the error floor is successfully suppressed down to BER of 10-12. An LDPC decoder using normalized min-sum variable-node-centric sequential scheduling decoding algorithm is implemented in UMC 90-nm CMOS process. The postlayout result shows that the proposed LDPC decoder can achieve a throughput of 1.58 Gb/s at six iterations with a gate count of 520k under a clock frequency of 166.6 MHz. It meets the throughput requirement of both NAND flash memories with Toggle double data rate 1.0 and open NAND flash interface 2.3 NAND interfaces.

As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.

To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of ηT pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller's loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller's loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 × 0.97 mm2. It performs a bilinear pairing computation over F(397) in 4.76 μs under 1.0 V supply and achieves 178% improvement to relative works in terms of area-time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3709) in 36.2 μs is implemented and this result is at least 31% better than relative works in terms of AT product.

This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1-24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60-84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.

This paper presents a non-binary LDPC decoder based on stochastic arithmetic. Although the previous stochastic works reduce the complexity of check node by transforming the convolution of the SPA algorithm to the finite field summation, the stochastic decoder still has a implementation bottleneck due to large storage introduced by the variable node process. Considering a balance between algorithm level and implementation level, we propose a shortened TFM architecture as well as its updating criterion. A compare-and-alter counter architecture is also proposed to avoid sorting among counters which decide the decoded codeword. With these features, the proposed (136, 68) fully-parallel stochastic NB-LDPC decoder over GF(32) implemented in UMC 90-nm can achieve 120 Mb/s throughput while operating under 455 MHz with 740 k gate counts which are only 10 % of the original TFM decoder.

This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.

Elliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4- mm2160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 μJ for one GF(p)/GF(2m) ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks.

This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.

The performance of LT code is highly related to the code length. A decoder is more likely to deplete degree-1 encoding symbols and terminate during early stage when the code length is short. In this work, we modify the robust Soliton distribution (RSD) and increase the degree-1 proportion. More degree-1 encoding symbols can be generated to relieve early decoding termination. The proportion of low degrees, except for degree-1, is also reduced. Therefore, receivers collect less encoding symbols carrying redundant information. In addition, Non-Repetitive (NR) encoding scheme is proposed to avoid producing repeated degree-1 encoding symbols. To improve video transmission quality, previous studies redesign LT codes to provide Unequal Error Protection (UEP) for different Scalable Video Coding (SVC) layers. Unlike those studies to modify the code structure, we integrate multiple NR encoders to achieve UEP ability. Experimental results show that our UEP scheme outperforms previous studies in terms of the PSNR.

Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.

A double error correcting (DEC) BCH codec is designed for NOR flash memory systems to improve reliability. Due to the latency constraint less than 10 ns, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Notice that encoder and decoder will not be activated simultaneously in NOR flash applications, so we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, a new error location polynomial is developed to reduce the number of constant finite filed multipliers (CFFMs) in Chien search. According to 90 nm CMOS technology, our propose DEC BCH codec can achieve 2.5 ns latency with 41,705 μm2area.

In order to support high speed application such as cloud computing, we propose a new elliptic curve cryptographic (ECC) processor architecture. The proposed processor includes a 3 pipelined-stage full-word Montgomery multiplier which requires much fewer execution cycles than that of previous methods. To reach real-time requirement, the time-cost pre-computation steps of Montgomery modular multiplication are achieved by hardware as well. Moreover, our proposed processor is resistant to the simple power analysis (SPA) attack by using the Montgomery ladder-based elliptic curve scalar multiplication (ECSM). Even the Montgomery ladder method inherently has operation overhead compared with traditional binary ECSM, both of hardware sharing and parallelization techniques are exploited to improve the hardware performance. Synthesized in TSMC 90nm CMOS technology, our proposed ECC processor performs a 256-bit ECSM in 120µs over prime field with 540K gate counts. This result is at least 25% better than relative works in terms of area-time (AT) product.

Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.

To enhance the data security in network communications, this paper presents a dual-field elliptic curve crypto- graphic processor (DECP) supporting all finite field operations and elliptic curve (EC) functions. Based on the fast radix-4 unified division algorithm, the execution time can be significantly reduced by a factor of three. By exploiting the hardware sharing and the ladder selection techniques, the proposed 160-bit and 256-bit DECP can have competitive execution cycle with only 0.29mm2and 0.45mm2silicon area in 90nm CMOS technology. In addition, the operating frequency in dual field can be increased by applying the data-path separation method and the degree checker. Our proposed DECP is over 2~6 times better in area- time product than relative works.

In existing soft decision algorithms, a soft BCH decoders provides better error correcting performance but has much higher hardware complexity than a traditional hard BCH decoder. In this paper, a soft BCH decoder with both better error correcting performance and lower complexity is presented. The low complexity feature of the proposed architecture is achieved by dealing with least reliable bits. By compensating extra one error outside the least reliable set, the error correcting ability is improved. In addition, the proposed error locator evaluator evaluates error locations without Chien search, leading to high throughput. As compared with the traditional hard BCH decoder, the experimental result reveals that our proposed improved soft BCH decoder can achieve 0.75db coding gain for BCH (255,239) code. Implemented in standard CMOS 90nm technology, it can reach 316.3Mb/s throughput at 360MHz operation frequency with gate-count of 4.06K according to the post-layout simulations.

To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.

A technique to prune the paths for K-best sphere decoding algorithm (SDA) based on radius constraint is presented. The proposed scheme preserves breadth-first searching nature, and the distinct radii for each decoding layer are theoretically derived from the system model with the noise statistics. In addition, based on the data range provided by the radius, a low complexity sorting strategy is proposed. The proposed method can apply to SDA with various path cost functions. Euclidean norm and sum of absolute difference are demonstrated in this paper. With SNR degradation less than 0.2 dB, more than 47% and 90% computation complexity can be reduced in 16-QAM and 64-QAM 4times4 MIMO detection, respectively.

Progressive edge-growth (PEG) algorithm was proven to be a simple and effective approach to design good LDPC codes. However, the Tanner graph constructed by PEG algorithm is non-structured which leads the positions of 1’s of the corresponding parity check matrix fully random. In this paper, we propose a general method based on PEG algorithm to construct structured Tanner graphs. These hardware-oriented LDPC codes can reduce the VLSI implementation complexity. Similar to PEG method, our CP-PEG approach can be used to construct both regular and irregular Tanner graphs with flexible parameters. For the consideration of encoding complexity and error floor, the modifications of proposed algorithm are discussed. Simulation results show that our codes, in terms of bit error rate (BER) or packet error rate (PER), outperform other PEG-based LDPC codes and are better than the codes in IEEE 802.16e.

The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different sub-matrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130 nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9 k and 37.4 k at 384 MHz operation frequency.

This paper presents a method for compensating the truncation error of fixed-width booth multipliers which keep the input and the output the same bit-width. The truncated part that produces the carry-out bits is replaced with a carry-estimation equation. In order to reduce the truncation error, different input-width multipliers will have different carry-estimation equations. Simulation results show that our self-compensation method can lead to 85 % reduction of truncation errors while compared with direct-truncated multipliers, as well as 40% reduction in area of a multiplier while compared with traditional booth multipliers. In contrast with the 128-point fast Fourier transform (FFT) using traditional booth multipliers, our approach has 10% area reduction but only 1 dB SQNR loss.

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.

We propose a new efficient serial architecture to implement the Berlekamp-Massey (1968, 1969) algorithm, which is frequently used in BCH and Reed-Solomon (1960) decoders. An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism. We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently. Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.

The Digital Versatile Disk (DVD) is an emerging standard to meet the ever increasing storage capacity requirement of future high quality video and audio applications. We implement a (208,192;8) Reed-Solomon decoder for the DVD Reed-Solomon product code (RS-PC). We propose a new area-efficient architecture which uses only three finite field multipliers (FFMs) to implement the inversionless Berlekamp-Massey (1968, 1979, 1969) algorithm. The error value evaluator employs an algorithm-based GF(2/sup m/) inverter instead of an inversion ROM-table. We implement the (208,192; 8) Reed-Solomon decoder using a 0.6 /spl mu/m SPDM CMOS technology with an area of 12.35 mm/sup 2/ (core area 6.45 mm/sup 2/). The chip can run at 16.67 MHz, while the DVD requirement is 3.74 MHz. A minor error was found in this first version which is corrected in the second version of the chip.