This paper describes GridSpice, a scalable open-source simulation framework for modeling, designing, and planning of the smart grid. GridSpice seamlessly integrates existing electric power simulation tools to enable modeling of large electric networks that blur the boundaries between generation, transmission, distribution, and markets. This is achieved via a cloud-based architecture that allows for parallelizing large simulation jobs across many virtual machines using a pay-as-you-go model. GridSpice simulations can be managed through a Representational State Transfer (REST) application programming interface (API), or through a Python library, allowing users to run simulations programmatically and interface with disparate data inputs, energy management systems (EMS), distribution management systems (DMS), and postprocessing tools. These capabilities make GridSpice an ideal tool for the development and testing of new grid control and optimization algorithms. GridSpice also provides an easy-to-use browser-based interface to allow novice users to begin without any setup or configuration on their local PC. A first implementation of the GridSpice framework integrates Gridlab-D and MATPOWER as simulation tools, and has been used for projects including optimizing the placement of distributed generation and developing optimal dispatch schedules for flexible loads. The GridSpice framework and Gridlab-D are freely available in open-source under the BSD license.

This paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. These situations are very common when the oscillator is part of a phase-locked loop (PLL). In PLLs, the reference frequency as well as the divide ratios are known at the time of design. Therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). We formulate this problem as the solution of an appropriate nonlinear equation. We present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. We demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. We show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.

Most embedded systems have limited amount of memory. In contrast, the memory requirements of code (in particular loops) running on embedded systems is significant. This paper addresses the problem of estimating the amount of memory needed for transfers of data in embedded systems. The problem of estimating the region associated with a statement or the set of elements referenced by a statement during the execution of the entire set of nested loops is analyzed. Aquantitative analysis of the number of elements referenced is presented; exact expressions for uniformly generated references and a close upper and lower bound for non-uniformly generated references are derived. In addition to presenting an algorithm that computes the total memory required, we discuss the effect of transformations on the lifetimes of array variables, i.e., the time between the first and last accesses to a given array location. A detailed analysis on the effect of unimodular transformations on data locality including the calculation of the maximum window size is discussed. The termmaximum window sizeis introduced and quantitative expressions are derived to compute the window size. The smaller the value of the maximum window size, the higher the amount of data locality in the loop.

h this paper, we proWse a new logic synthesis methodology to deal with the increasing imprtance of the interconnect delay in deepsubmicron technologies.We first show that conventional logic synthesis techniques can produce circuits which wi~have long paths even if placed optimally.Then, we charactetie the conditions under which this cm happen and propose logic synthesis techniques which pmduw circuits which are "bettefl for placement.Our proposed approach still separates logic synthesis from physical design.

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multistage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. They show that the proposed approach allows one to make logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do nor have any equivalent in the traditional approach. They also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that the technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of their knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

We address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of partitioned ROBDDs to reduce the memory explosion problem associated with symbolic state space exploration techniques. In our technique, the reachable state set is represented as a partitioned ROBDD (A. Narayan et al., 1996). Different partitions of the Boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. We show the effectiveness of our approach on a set of ISCAS89 benchmark circuits. Our techniques result in a significant reduction in total memory utilization. For a given memory limit, partitioned ROBDD based method can complete traversal for many circuits for which monolithic ROBDDs fail. For circuits where both partitioned ROBDDs as well as monolithic ROBDDs cannot complete traversal, partitioned ROBDDs can reach a significantly larger set of states.

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. The authors survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. They classify the current approaches for combinational verification into two categories: functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. They briefly describe some of the methods in both the categories and discuss their merits and drawbacks.

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We present a new representation for Boolean functions called Partitioned ROBDDs. In this representation we divide the Boolean space into 'k' partitions and represent a function over each partition as a separate ROBDD. We show that partitioned-ROBDDs are canonical and can be efficiently manipulated. Further they can be exponentially more compact than monolithic ROBDDs and even free BDDs. Moreover, at any given time, only one partition needs to be manipulated which further increases the space efficiency. In addition to showing the utility of partitioned-ROBDDs on special classes of functions, we provide automatic techniques for their construction. We show that for large circuits our techniques are more efficient in space as well as time over monolithic ROBDDs. Using these techniques, some complex industrial circuits could be verified for the first time.