Reconfigurable radio frequency (RF) system has recently emerged as a promising solution to cope with multiple communication standards and high spectrum density. In this paper, we propose a novel optimization framework to efficiently program a reconfigurable RF system. In particular, two novel techniques, including (i) search space reduction by adaptive resolution and (ii) global polynomial optimization based on branch and bound, are developed. When combined with a relaxation iteration scheme, our proposed method offers superior performance when programming a large-scale reconfigurable RF system designed for the WLAN 802.11g standard.

Reconfigurable radio frequency (RF) system has emerged as a promising avenue to achieve high communication performance while adapting to versatile commercial wireless environment. In this paper, we propose a novel technique to optimally program a reconfigurable RF system in order to achieve maximum performance and/or minimum power. Our key idea is to adopt an equation-based optimization method that relies on general-purpose, non-convex polynomial performance models to determine the optimal configurations of all tunable circuit blocks. Most importantly, our proposed approach guarantees to find the globally optimal solution of the non-convex polynomial programming problem by solving a sequence of convex semi-definite programming (SDP) problems based on convexification. A reconfigurable RF front-end example designed for WLAN 802.11g demonstrates that the proposed method successfully finds the globally optimal configuration, while other traditional techniques often converge to local optima.

Passive macromodeling for RF circuit blocks is a critical task to facilitate efficient system-level simulation for large-scale RF systems (e.g., wireless transceivers). In this paper we propose a novel algorithm to find the optimal macromodel that minimizes the modeling error based on measurement data, while simultaneously guaranteeing passivity. The key idea is to attack the passive macromodeling problem by solving a sequence of convex semi-definite programming (SDP) problems. As such, the proposed method can iteratively find the optimal poles and zeros for macromodeling. Our experimental results with several commercial RF circuit examples demonstrate that the proposed macromodeling method reduces the modeling error by 1.31-2.74× over other conventional approaches.

In order to support a multi-standard platform, a reconfigurable RF front-end needs an optimal configuration that adapts to a dynamic communication condition. To find an optimal configuration efficiently, we previously proposed the Environment-Adaptable Fast (EAF) optimization in terms of the RF impairments of gain, nonlinearity and noise figure. However, this preliminary study did not include the important impairment of phase noise. In this paper, we extend the EAF optimization algorithm to phase noise impairment in a reconfigurable RF front-end. In this study, we will propose a novel statistical estimation tool for obtaining phase noise spectrum information with the Interpolated FIR (IFIR) model and the least mean squares (LMS) adaptive algorithm. We formulate the calculation of the Signal-to-Interference-and- Noise Ratio (SINR) which hastens the optimization process. Phase noise is included in the SINR calculation. We demonstrate the efficient performance of the EAF optimization method even with phase noise impairment. This study shows that while finding an optimal configuration, the EAF optimization significantly reduces simulation time compared to the other four conventional optimization methods.

Reconfigurable radio frequency (RF) system is an emerging component to mitigate the growing engineering cost for wireless chip design. In this paper, we propose a new methodology for efficient programming of reconfigurable RF receiver. The proposed method is facilitated by two novel techniques: two-phase relaxation search and Pareto-based search space reduction. Our numerical experiments demonstrate that the proposed methodology is more robust (i.e., close to global optimum) and/or efficient (i.e., with low computational cost) than other traditional algorithms based on either local relaxation or simulated annealing.

Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we describe a novel technique of adaptive post-silicon tuning to reliably design MEMS filters that are robust to process variations. Our key idea is to implement a number of redundant MEMS resonators to form an array and then optimally select a subset of these resonators to achieve the desired frequency response. Several new CAD algorithms and methodologies are proposed to optimize and configure the design variables of the proposed MEMS resonator array. A MEMS design example demonstrates that the proposed post-silicon tuning is able to reduce the ripple of the channel filter gain by 7x over other traditional approaches.

An RF ranging sensor based on time-interleaved Dual Frequency Continuous Wave (DFCW) radar is proposed to measure the absolute distance between two shoes to aid a dead reckoning system for pedestrian navigation. Conventional single frequency Continuous Wave (CW) radar provides accurate but ambiguous range measurement, while DFCW techniques are employed to find the approximate range of the target and to remove the ambiguity of the single frequency CW radar. The two frequencies in the proposed DFCW radar work in a Time division Duplexing (TDD) manner so that they can share the same transceiver hardware. Such a composite DFCW/CW system can be implemented with a simple direct conversion receiver which is desirable for applications such as pedestrian navigation where compact and low power consumption devices are required. The feasibility of the proposed sensor is demonstrated by a sensor prototype based on Commercial Off The Shelf (COTS) components in a practical environment. An absolute accuracy (RMS) of 0.92 mm has been achieved for a maximum test range of 600 mm. The results show that the proposed ranging sensor is promising for measuring the distance in short range applications.

Biotechnologists have started to exploit the semiconductor industry's planar microfabrication technology. This talk reviews the state of the art in planar biofluidic microdevices. Design aids needed for this emerging area are motivated. A place and route approach that simultaneously considers both the physical design of the chip as well as the physical constraints on device performance is introduced. Capillary electrophoretic separation based bioanalysis subsystems such as those needed for DNA sequencing are designed using this approach. The focus is on chips that integrate multiple parallel analysis subsystems to improve biosensing specificity and sensitivity. A roadmap for extending this to fully integrated biofluidic microchips that contain mixing, reaction, injection and detection subsystems is described

Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. Thefirst generation design was fabricated in a 0.35 μm SiGe BiCMOS process. It has a measured peak S21 of 17 dB and noise figure less than 3 dB over a bandwidth of 2.6 GHz while consuming 32.5 mW of power from a 2.5 V supply. The calculated figure of merit (FOM) is better than many reported wideband LNAs, including a few from even more advanced processes. The synthesis design constraints were improved based on the analysis of the first gener-ation design. A second generation design was synthesized with the updated constraints. Its simulation results show that its FOM is better than its predecessor.

Lab-on-a-chip (LoC) systems can be functionally decomposed into their basic operating devices. Common devices are mixers, reactors, injectors, and separators. In this paper, the injector device is modeled using artificial neural networks (NNs) trained with finite element simulations of the underlying mass transport partial differential equations (PDEs). This technique is used to map the injector behavior into a set of analytical performance functions parameterized by the system's physical variables. The injector examples shown are the cross, the double-tee, and the gated-cross. The results are four orders of magnitude faster than numerical simulation and accurate with mean square errors (MSEs) on the order of$10^-4$. The resulting NN training data compare favorably with experimental data from a gated-cross injector found in the literature.

Lab-on-a-chip (LoC) devices are a class of microfluidic chip-based systems that show a great deal of promise for complex chemical and biological sensing and analysis applications. An approach for full-custom LoC design, which leverages optimal design techniques and system-on-a-chip (SoC) physical design methods, is being developed. Both physical design of the chip and microfluidic performance are simultaneously considered to obtain complete LoC layouts. The proposed approach is demonstrated by designing multiplexed capillary electrophoresis (CE) separation microchips. The authors believe that this approach provides a foundation for future extension to LoC devices in which many different complex chemical operations are performed entirely on-chip.

This paper presents composable behavioral models and a schematic-based simulation methodology to enable top-down design of electrokinetic (EK) lab-on-a-chip (LoC). Complex EK LoCs are shown to be decomposable into a system of elements with simple geometry and specific function. Parameterized and analytical models are developed to describe the electric and biofluidic behavior within each element. Electric and biofluidic pins at element terminals support the communication between adjacent elements in a simulation schematic. An analog hardware description language implementation of the models is used to simulate LoC subsystems for micromixing and electrophoretic separation. Both direct current (dc) and transient analysis can be performed to capture the influence of system topology, element sizes, material properties, and operational parameters on LoC system performance. Accuracy (relative error generally less than 5%) and speedup$(≫hbox100times)$of the schematic-based simulation methodology are demonstrated by comparison to experimental measurements and continuum numerical simulation.

The paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 /spl mu/m CMOS process.

Biotechnologists have started to exploit the IC industry's planar microfabrication technology. The state of the art in planar biofluidic microdevices is reviewed as a way of introducing biochip design issues. As with transistor ICs, design aids that span the entire ICCAD program from modeling and simulation to synthesis and physical design are needed to address these issues. Hierarchical design representations, modeling abstractions, and algorithms pertaining to biochip design will be reviewed. Potential future challenges will be identified to motivate how the ICCAD community can contribute to this emerging area.

As design of integrated microelectromechanical systems (MEMS) mature, there is an increasing need for verification tools for such mixed-domain layouts. This requires a mixed-domain layout-versus-schematic tool capable of extracting an integrated schematic from the mixed-domain layout and verifying it against the design schematic. This paper reports on a prototype implementation of such a tool and an extraction methodology for integrated MEMS designs capable of capturing domain-specific parasitics. A custom schematic-versus-schematic tool is then used to compare the parameters and connectivity of schematic elements between the extracted and design schematic. Finally, simulation of the extracted schematic is used to analyze the behavior of the designed layout.

Microchip structures represent an attractive platform for microscale chemical processing of fluidic systems. However, standardized design methods for these devices have not yet been developed. Here we describe our work toward adapting traditional SoC circuit design techniques for the synthesis of fully customized and multiplexed lab-on-a-chip (LoC) devices. We discuss our formulation of the multiplex layout problem and present an approach for the design of microchip based electrophoretic separation systems. This work is extendable to systems incorporating mixing and reaction.

The long term impact of MEMS technology will be in its ability to integrate novel sensing and actuation functionality on traditional computing and communication devices enabling the ubiquitous digital computer to interact with the world around it. The design and verification of such integrated systems will occur at the system level, driven primarily by the application. Application-driven systemlevel design methodologies that ease the integration of the digital domain to the real world using mixed domain technologies are therefore needed. A hierarchical structured approach that is compatible with standard IC design is outlined. It starts with schematic capture of a design topology, followed by behavioral simulation, layout generation, parasitic extraction, and final verification.

As design of integrated MicroElectroMechanical Systems (MEMS) matures, there is an increasing need for verification of MEMS layouts. This requires a mixed-domain LVS (layout-versus-schematic) methodology capable of extracting an integrated schematic from the mixed-domain layout and verifying it against the designed schematic. This paper reports on a prototype implementation of MEMS LVS and a MEMS extractor, which, in addition to reconstructing the extracted schematic also captures the domain-specific parasitics in the individual devices. This schematic is then used by a custom schematic-versus-schematic comparator to match connectivity of various elements between the designed and extracted schematics. Finally, simulation of the extracted schematic also helps in capturing the true behavior of the system.

Schematic-based lumped parameterized behavioral modeling and simulation methodologies have become available since the emergence of analog HDLs. They greatly ease iterative hierarchical multi-domain simulation, which is critical to the design of MEMS. NODAS is one of such tools, with models written in VerilogA and simulation performed within the Cadence framework.This paper focuses on several key modeling issues in NODAS, including schematic representation, element communication, linear, nonlinear and multi-domain modeling, and extensibility to new physical effects, processes and physical domains. A nonlinear beam model and an electrostatic gap model are discussed as examples. Simulation comparison to finite element analyses and experimental data verifies the accuracy of the models and validates the simulation methodology.

We describe a synthesis system that takes operating range constraints and inter and intracircuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to computer-aided design for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an infinite programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints. And finally, we show that our consideration of variations during the initial optimization-based circuit synthesis leads to better starting points for post-synthesis yield optimization than a classical nominal synthesis approach.

In this survey paper, we describe and contrast three different approaches for extending circuit simulation to include micromachined devices. The most commonly used method, that of using physical insight to develop parameterized macromodels, is presented first. The issues associated with fitting the parameters to simulation data while incorporating design attribute dependencies are considered. The numerical model order reduction approach to macromodeling is presented second, and some of the issues associated with fast solvers and model reduction are summarized. Lastly, we describe the recently developed circuit-based approach for simulating micromachined devices, and describe the design hierarchy and the use of a catalog of parts.

In order to efficiently design complex microelectromechanicalsystems (MEMS) having large numbers of multi-domain components,a hierarchically structured design approach that iscompatible with standard IC design is needed. A graphical-basedschematic, or structural, view is presented as a geometrically intuitiveway to represent MEMS as a set of interconnected lumped-parameterelements. An initial library focuses on suspended-MEMStechnology from which inertial sensors and other mechanicalmechanisms can be designed. The schematic representationhas a simulation interface enabling the designer to simulate thedesign at the component level. Synthesis of MEMS cells for commontopologies provides the system designer with rapid, optimizedcomponent layout and associated macro-models. Asynthesis module is developed for the popular folded-flexuremicromechanical resonator topology. The algorithm minimizes acombination of total layout area and voltage applied to the electromechanicalactuators. Synthesis results clearly show the designlimits of behavioral parameters such as resonant frequency for afixed process technology.

We describe a synthesis system that takes operating range constraints and inter- and intra-circuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to CAD for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an Infinite Programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints.