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Jörg Hilgenstock

dblp:40/6217 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Parallel and multicore computing · 50%
Computer graphics and multimedia
1 paper
Image and video coding · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › video processing accelerator
video signal processor
0.011998
A Video Signal Processor for MIMD Multiprocessing · DAC 1998
Image and video coding
video compression
0.011998
A Video Signal Processor for MIMD Multiprocessing · DAC 1998

Methods — techniques the papers use, named apart from their topics

coprocessor design · 0.0RISC · 0.0
YearPublicationVenuePosition
2008 Nighttime Vehicle Detection for Intelligent Headlight Control
Antonio M. López 0001, Jörg Hilgenstock, Andreas Busse, Ramón Baldrich, Felipe Lumbreras, Joan Serrat 0002
ACIVS2
1999 Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM
abstract
A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.
Jörg Hilgenstock, Klaus Herrmann 0002, Peter Pirsch
Great Lakes Symposium on VLSI1
1998 A Video Signal Processor for MIMD Multiprocessing
abstract
The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263, and ISO MPEG-1/2.Itconsists of a RISC processor supplemented by a coprocessor forconvolution-like low-level tasks.RISC and coprocessor have beenimplemented in a standard cell design combined with full-custommodules.The processor was fabricated in a 0.5 µm CMOS technologyand has a die size of 82 mm{2}.It provides a peak performanceof more than 1 giga arithmetic operations per second (GOPS) at66 MHz.For processing of very computation-intensive algorithmsor high data rates, several processors can be bus-connected to forma MIMD multiprocessor system.
Jörg Hilgenstock, Klaus Herrmann 0002, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch
DAC1