Integrated circuit design in millimeter-wave (mm-Wave) bands is exceptionally complex and dependent on costly electromagnetic (EM) simulations. Therefore, in the past few years, a growing interest has emerged in developing novel optimization-based methodologies for the automatic design of mm-Wave circuits. However, current approaches lack scalability when the circuit/system complexity increases. Besides, many also depend on EM simulators, which degrade their efficiency. This work resorts to hierarchical system partitioning and bottom-up design approaches, where a precise machine learning model - composed of hundreds of seamlessly integrated sub-models that guarantee high accuracy (validated against EM simulations and measurements) up to 200GHz - is embedded to design passive components, e.g., transformers and baluns. The model generates optimal design surfaces to be fed to the hierarchical levels above or acts as a performance estimator. With the proposed scheme, it is possible to remove the dependency of EM simulations during optimization. The proposed mixed-optimal-surface, performance estimator, and simulation-based bottom-up multiobjective optimization (MOO) are used to fully design a Ka-band mm-Wave transmitter from the device up to the system level in 65-nm CMOS for state-of-the-art specifications.

This work presents a 16MHz on_chip oscillator based on a frequency_locked loop (FLL) which is radiation hardened by design and intended for space applications. The oscillator maintains a high temperature stability over a wide range oftemperatures, process and voltage variations. The FLL presents a 7-stage current starved ring oscillator using output signal combiners for lower radiation sensitivity. Furthermore, the system presents high reconfigurability by using several DACs to adjust the oscillator’s output frequency and the temperature slope dependency. This reconfigurability is especially useful to maintain all performances across PVT variations.

The automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks in deep nanometer technologies has moved towards process, voltage, and temperature (PVT)-inclusive optimizations, to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations’ capabilities to their limits. This paper presents innovative research towards the automation of RF IC design by using deep learning to assist the simulation-based sizing tools in time-consuming PVT-inclusive optimizations. The proposed PVT regressor inputs the circuit’s sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. The proposed controlled PVT estimator is tested on a state-of-the-art class C/D voltage-controlled oscillator, reducing the workload of the circuit simulator up to 79% while achieving a speed-up factor of $2.92 \times $, ultimately saving more than 16 days of computational effort.

The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder-decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder-decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder-only, decoder-only, and encoder-decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

Dispatching rules are simple but efficient heuristics to solve multi-objective job shop scheduling problems, particularly useful to face the challenges of dynamic shop environments. A promising method to automatically evolve non-dominated rules represents multi-objective genetic programming based hyper-heuristic (MO-GP-HH). The aim of such methods is to approximate the Pareto front of non-dominated dispatching rules as good as possible in order to provide a sufficient set of efficient solutions from which the decision maker can select the most preferred one. However, one of the main drawbacks of existing approaches is the computational demanding simulation-based fitness evaluation of the evolving rules. To efficiently allocate the computational budget, surrogate models can be employed to approximate the fitness. Two possible ways, that estimate the fitness either based on a simplified problem or based on samples of fully evaluated individuals making use of machine learning techniques are investigated in this paper. Several representatives of both categories are first examined with regard to their selection accuracy and execution time. Furthermore, we developed a surrogate-assisted MO-GP-HH framework, incorporating a pre-selection task in the NSGA-II algorithm. The most promising candidates are consequently implemented in the framework. Using a dynamic job shop scenario, the two proposed algorithms are compared to the original one without using surrogates. With the aim to minimize the mean flowtime and maximum tardiness, experimental results demonstrate that the proposed algorithms outperform the former. Making use of surrogates leads to a reduction in computational costs of up to 70%. Another interesting finding shows that the enhanced ability to identify duplicates based on the phenotypic characterization of individuals is particularly helpful in increasing diversity within a population. This study illustrates the positive effect of this mechanism on the exploration of the entire Pareto front.

In this paper, disruptive research using modern embedding techniques and an attention-based encoder-decoder deep learning (DL) model is conducted to automate analog layout synthesis. Unlike previous legacy-based placement automation mechanisms, the attention-based Graph2Seq model is inherently independent of the number of devices within a circuit topology and their order. Moreover, its unsupervised training does not rely on expensive legacy layout data but only on sizing solutions. Experimental results show that the proposed model generates placement solutions at push-button speed and can generalize to circuit topologies and technological nodes not used in training. Moreover, while being scalable, the model produces placement solutions that compete with highly optimized analog placements and other, order-dependent and non-scalable, DL models.

This paper presents an innovative approach toward the automation of the placement task of analog integrated circuit layout design by using an artificial neural network that generates multiple valid floorplan solutions at push-button speed. The proposed model extends the knowledge mining of the most recent layout generation techniques as an end-to-end approach. A novel loss function is used in a semi-supervised fashion for the model to learn how to generate effective placements that follow topological constraints instead of simply trying to copy devices' locations from some pre-existing labeled dataset of placement solutions. Thus, in addition to eliminating the need for a large dataset of placed sizing solutions for training, the model generalizes better and outputs better layouts for solutions outside the training set. Moreover, one step further is taken towards a model that can predict the placement of different circuit topologies by supporting different encodings (with different number of devices) on the input layer of the artificial neural networks, ultimately fostering an opportunity to reuse incomplete legacy layout information. As proof of concept, the one ANN trained for 2 amplifier topologies is used to produce multiple placement recommendations in less than 40 ms for new designs.

This paper presents fuzzy c-means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the automatic sizing of radio frequency integrated circuit blocks, where an all-inclusive test bench formulation enhanced with an additional measurement processing system enables the optimization of “everything at once” toward its true optimal tradeoffs. VCOs embedded in the state-of-the-art multistandard transceivers must comply with extremely high performance and ultralow power requirements for modern cellular and Internet of Things applications. However, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches, and/or analysis must be considered simultaneously. Here, the dual-mode design and optimization conducted provided 287 design solutions with figures of merit above 192 dBc/Hz, where the power consumption varies from 0.134 to 1.333 mW, the phase noise at 10 MHz from -133.89 to -142.51 dBc/Hz, and the frequency pushing from 2 to 500 MHz/V, on the worst case of the tuning range. These results pushed this circuit design to its performance limits on a 65-nm CMOS technology, reducing 49% of the power consumption of the original design while also showing its potential for ultralow power with more than 93% reduction. In addition, worst case corner criteria were also performed on the top of the worst case tuning range optimization, taking the problem to a human-untrea table LXVI-D performance space.

State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume.

In this work we propose to use Twitter to find companies with a good growth potential that could be good investment options. In order to achieve this we built a sentiment model using the text content of tweets. We make use of hashtags to collect Twitter posts from a broad range of emotions so that our sentiment model can reliably distinguish tweets containing different sentiment expressions. To guarantee that no human sentiment is left behind we adopted emotions from the Circumplex Model of Affect and their synonyms and used them as search terms on the Twitter API. Afterwards, we use those tweets with a support vector machine (SVM) classifier to build a sentiment model. This model was used to classify company related tweets in order to predict the predominant sentiment in them. With the sentiment measures of tweets from different companies we created a trading rule that was optimized by a Genetic Algorithm (GA) so that we can maximize profit. Our simulations show that using the rules we implemented it is possible to build a profitable strategy for trading in the stock market using Twitter with the rules we implemented. During our testing period (November 7, 2016 to December 16, 2016) we achieved a 11% return, outperforming the S&P 500, NASDAQ 100 and DJIA composites.

This paper addresses the problem of automatic technology migration of analog IC designs. The proposed method introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit classes. In addition to technology independence, reusing the testbenches when adding new topologies for the already implemented circuit classes also improves design productivity. The new method is implemented and tested using a state-of-the-art multi-objective multi-constraint circuit-level optimization tool for circuit sizing, and is validated for the design and optimization of continuous-time comparators, including technology migration between two different design nodes, respectively, XFAB 350 nm technology and ATMEL 150 nm SOI technology.

This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.

Swarm intelligence algorithms are amongst the most efficient approaches toward solving optimization problems. Up to now, most of swarm intelligence approaches have been proposed for optimization in static environments. However, numerous real-world problems are dynamic which could not be solved using static approaches. In this paper, a novel approach based on artificial fish swarm algorithm (AFSA) has been proposed for optimization in dynamic environments in which changes in the problem space occur in discrete intervals. The proposed algorithm can quickly find the peaks in the problem space and track them after an environment change. In this algorithm, artificial fish swarms are responsible for finding and tracking peaks and several behaviors and mechanisms are employed to cope with the dynamic environment. Extensive experiments show that the proposed algorithm significantly outperforms previous algorithms in most of tested dynamic environments modeled by moving peaks benchmark.

This paper presents a thermal-aware floorplaning tool for integrated MOSFET power stages. It generates area and power optimized transistors, automatically complying with design rules. The tool also creates placement solutions of power stages, optimizing for area, wire-length and temperature spread. The tool creates technology independent layouts, and directly export designs into GDSII format, allowing complete independence from IC design platforms. A brief comparison of floorplanning techniques, embedded in this tool, is presented for several generally known benchmarks. The device layout and thermal-aware floorplaning capabilities are demonstrated and compared with manual designs of a half-bridge power stage for a Class-D amplifier, and a manually optimized device layout in a DC-DC buck converter stage - the tool results exhibit lower resistance and dynamic power losses while speeding-up the design flow by orders of magnitude.

In this paper an innovative routing methodology considering wiring symmetry (WS) for multiport multiterminal (MP/MT) signal nets of analog and mixed-signal integrated circuits (ICs) is presented. In our work, first, an electromigration (EM)-aware wiring topology for each power and signal network is constructed directly from the netlist, and then, several embedded symmetry rules between wires are automatically identified and applied in the global and detailed routing phases. The use of such MP terminals strongly enhances both the ability to route the circuit and the WS. The design flow is demonstrated for the UMC 130nm design process.

In this paper, the current starving technique is applied to a voltage-combiners-biased symmetrical CMOS Operational Transconductance Amplifier (OTA). The proposed topology upgrade enhances the gain of the conventional topology, improves the settling time by means of enhancing its gain-bandwidth product and highly improves its energy efficiency. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 60 dB can be achieved together with a high energy efficiency (a figure-of-merit of 2200 MHz×pF/mA has been reached). The circuit was designed using a standard 130 nm CMOS technology and drains less than 0.5 mA from a 3.3 V power supply.

This work presents a new approach to portfolio composition in the stock market. It incorporates a fundamental approach using financial ratios and technical indicators with a Multi-Objective Evolutionary Algorithms to choose the portfolio composition with two objectives the return and the risk. Two different chromosomes are used for representing different investment models with real constraints equivalents to the ones faced by managers of mutual funds, hedge funds, and pension funds. To validate the present solution two case studies are presented for the SP&500 for the period June 2010 until the end of 2012. The simulations demonstrate that stock selection based on financial ratios is a combination that can be used to choose the best companies in operational terms, obtaining returns above the market average with low variances in their returns. In this case the optimizer found stocks with high return on investment in a conjunction with high rate of growth of the net income and a high profit margin. To obtain stocks with high valuation potential it is necessary to choose companies with a lower or average market capitalization, low PER, high rates of revenue growth and high operating leverage.

This paper describes an electromigration-aware and IR-Drop avoidance routing approach considering multiport multiterminal (MP/MT) signal nets of analog integrated circuits (IC). The effects of current densities and temperature in the interconnects may cause the malfunction/failure of a circuit due to IR-Drop or electromigration (EM). These become increasingly more relevant with the ongoing reduction of circuit sizes caused by the evolution of the nanoscale integration processes. Therefore, EM and IR-Drop effects must be taken into account in the design of both power networks and signal wires of analog and mixed-signal ICs, to make their impact on the circuits' reliability negligible. In previous EM and IR-Drop-aware analog IC routing approaches, `dot-models' are assumed for the terminals, i.e., each terminal has only one port that need to be routed, however, in practice, analog standard cells usually contain multiple electrically-equivalent locations, often distributed over different fabrications layers, where legal connections can be made, i.e., MP terminals, which need to be properly explored. The design flow is detailed, and the applicability of the approach is demonstrated with experimental results, and also, by generating the routing of an analog circuit structure for the UMC 130 nm design process.

Typically the design of oscillators is done aiming at both minimum phase noise and minimum power consumption, however, these two objectives are contradictory. Yet, this tradeoff, which is also the base for the definition of the figure of merit of oscillators, is seldom explored is previous publications. In this paper, an LC-Voltage Controlled Oscillator (VCO) was considered in a multi-objective optimization process, where the accuracy and reliability of the solution is guaranteed by the usage of a circuit simulator to evaluate the circuit performance. The state-of-the-art circuit optimization tool AIDA-C was used in the automatic synthesis of the LC-VCO, obtaining a set of about 40 design solutions with FOM bellow -191 dBc/Hz, where the power consumption varies from 0.22 to 0.46 mW and the phase noise varies from -120.47 to -116.72 dBc/Hz.

In the state-of-the-art on analog integrated circuit (IC) automatic routing approaches it is assumed that each terminal has only one port that can be routed, however, in practice a device usually contains multiple electrically-equivalent locations where the connection can be made, multi-port terminals, which are not properly explored. This paper describes an innovative evolutionary approach with multi-port multiterminal (MP/MT) nets for analog IC automatic routing. The netlist and the multi-port terminals are modeled in a Group-Steiner problem that is solved by the Global Router, to obtain the terminal-to-terminal connectivity, and then, for the detailed routing, an optimization kernel is used, namely, an enhanced version of the multi-objective evolutionary algorithm NSGA-II. The Router starts by a single-net procedure, and culminates in a process where all nets are optimized simultaneously. The technology design rules are verified during the evolutionary generation using an in-loop built-in layout evaluation procedure. The automatic routing generation is detailed, and demonstrated for the generation of the layout of a typical analog circuit, for the UMC 130nm design process. The automatically generated layouts are validated using the industrial grade Calibre®tool and the performances of the extracted circuits are compared with the ones achieved in the circuit-level design.

This paper presents a new approach to enhance a state-of-the-art layout-aware analog IC circuit-level optimizer, by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on a modified NSGA-II algorithm. The gradient model is automatically generated by, first, using a design of experiments (DOE) approach with two alternative sampling strategies, the full factorial design and the fractional factorial design, which define the samples that will be accurately evaluated using a circuit simulator (e.g. HSPICE®), second, extracting and ranking the contributions of each design variable to each performance measure or objective, and, finally, building the model based on series of gradient rules. The gradient model is then embedded into the modified NSGA-II optimization kernel, by acting on the mutation operator. The approach was validated with typical analog circuit structures for an industry standard 0.13 μm integration process, showing that, by enhancing the circuit sizing evolutionary kernel with the gradient model, the optimal solutions are achieved, considerably, faster and with identical or superior accuracy.

This paper presents the design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz-pF/mA has been achieved).

This paper describes an innovative design automation tool, LAYGEN II, for analog integrated circuit (IC) layout generation based on template descriptions and on evolutionary computation techniques. LAYGEN II was developed giving special emphasis to the reusability of expert knowledge and to the efficiency of retargeting operations. The designer specifies the sized circuit-level structure, the required technology and also, the layout template consisting of technology and specification independent high-level layout guidelines. For placement, the topological relations present in the template are extracted to a nonslicing B*-tree layout representation, and the tool automatically merges devices and improves the floorplan quality. For routing an optimization kernel consisting of a tailored version of the multiobjective multiconstraint evolutionary algorithm NSGA-II is used. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.

This paper presents a new computational finance approach, combining a Symbolic Aggregate approXimation (SAX) technique together with an optimization kernel based on genetic algorithms (GA). The SAX representation is used to describe the financial time series, so that, relevant patterns can be efficiently identified. The evolutionary optimization kernel is here used to identify the most relevant patterns and generate investment rules. The proposed approach was tested using real data from S&P500. The achieved results show that the proposed approach outperforms both B&H and other state-of-the-art solutions.

In this paper, a multi-objective design methodology and tool for automatic analog IC synthesis, which takes into account the effects of process variations, is presented. By varying the technological and environmental parameters, the robustness of the solutions is enhanced. The automatic analog IC sizing tool, GENOM-POF, was implemented to demonstrate the methodology and to verify the effects of corner cases on the Pareto optimal front (POF). The impacts of NSGA-II parameters when applied to analog circuit sizing were investigated, and three different design strategies were tested in a benchmark circuit, showing the effectiveness of multi-objective design of analog cells.

This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technology, and can be used hierarchically in the definition of templates for complex circuits. LAYGEN II uses this expert knowledge to guide the evolutionary optimization kernels during the automatic layout generation in the target technology. The routing task of the proceeding can range from a template-based approach to a full automatic generation, if only connectivity is provided. The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre® design rule check tool.

This paper describes a new computational finance approach. This approach combines pattern recognition techniques with an evolutionary computation kernel applied to financial markets time series in order to optimize trading strategies. Moreover, for pattern matching a template-based approach is used in order to describe the desired trading patterns. The parameters for the pattern templates, as well as, for the decision making rules are optimized using a genetic algorithm kernel. The approach was tested considering actual data series and presents a robust profitable trading strategy which clearly beats the market, S&P 500 index, reducing the investment risk significantly.

This paper describes an innovative analog circuit design optimization kernel. The new approach generates fuzzy models for qualitative reasoning based on a DOE approach. The models are then used within a standard genetic algorithm implementation enhancing the search by incorporating design knowledge represented by the fuzzy models. The achieved performance is discussed for a set of well known analog circuit structures.

This paper presents a multi-standard reconflgurable sigma-delta modulator, which is able to support the predictable standards of fourth generation of mobile communication systems (4G). Furthermore, the proposed architecture halves the number of required analog-to-digital converters in parallel receivers, by processing concurrently two different signals. The major design issues are outlined and operation modes are detailed. A system-level simulation is performed to demonstrate the feasibility of the presented solution. The modulator is implemented into switched-capacitor circuits and device level simulations demonstrate the performance of the converter.

This paper describes an innovative analog IC layout generation approach based on evolutionary computation techniques.

An efficient use of macromodeling techniques is pointed out as an effective approach to improve the convergence and speed of the optimization process. The methodology presented in this paper is based on a learning scheme using Support Vector Machines(SVMs) that together with and an evolutionary strategy is used to create efficient models to estimate and optimize the performance parameters of analog and mixed-signal ICs. The SVM is used to identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization based methodology is demonstrated for the design of a well known class of CMOSoperational amplifier topologies. The efficiency of the proposed approach is compared with standard and modified genetic algorithm kernels.

The generalized use of e-learning platforms both on campus and on distance learning scenarios promote a widespread dissemination of information among the users, however, an effective loss of "face-to-face" contact between tutor and student occurs. In this paper, a new 3-level classification model for tracking analysis on e-learning platforms is presented. In order to adopt this 3-level model a new data management system is introduced allowing the implementation of an information support system, an intelligent tutoring system and a decision support system, this way, improving the learning efficiency and overcoming the lack of "face-to-face" contact in previous e-learning approaches.

Nowadays, the leading e-learning platforms are converging towards standardization. This paper presents an extension to the SCORM e-learning standard, enabling the modelling of course related entities that surround learning objects and content aggregations, therefore increasing the standard's modelling scope and course portability. A prototype is being implemented and tested on VIANET, an original SCORM enabled e-learning platform.

VIANET, a new Web framework addressing the distance learning scenario is presented. The VIANET project aims at bringing together the most promising Web technologies and standards, in order to attain a highly competitive online learning environment. Moreover, the new Web framework includes a learning management system (LMS), a SCORM based learning content management system (LCMS) and a virtual class system supporting the innovative solutions taken to implement reusability, portability, scalability, data warehousing, groupware and standardization.

This paper describes the automatic generation and reusability of physical layouts of analog and mixed-signal blocks based on high-functionality pCells that are fully independent of technologies. The high-functionality pCell library presently contains over 42 pCells and is fully compliant with 7 different sets of technology design rules from 5 different foundries. Practical examples employed in industrial projects are illustrated.

This paper discusses the use of symbolic methods applied to the design automation of SI data converters. The proposed approach is an extension of an already proved methodology, for the symbolic synthesis of linear and nonlinear data converters. This is performed by introducing SI characteristics in modified signal flow graph representation of conversion algorithms, including a new set of functional and electrical structures in the system library and, finally, defining an appropriate sizing mechanism for the new structures. The design process is here exemplified for a well known data conversion algorithm.

A new, algorithm-driven methodology is introduced for the synthesis of data conversion systems. It employs a combination of symbolic signal flow graph techniques to generate a canonical representation of the algorithm description, together with pattern recognition techniques, to determine the appropriate functional building blocks for the converter architecture and knowledge-based rules to instantiate such building blocks by electrical subcircuits. By allowing the synthesis process to move to higher levels of abstraction the proposed methodology provides a computer-based framework for the systematic and uniform treatment of various types of conversion systems, including the search for new conversion algorithms and/or new implementation architectures.

A methodology for automatic generation of data conversion topologies from algorithms is described. Based on the symbolical manipulation of the corresponding analog-digital graph representation, the analog and digital graph partitions are first translated into a set of functional building blocks and a state machine, respectively. The final conversion system topology is determined by instantiating the identified functional blocks with the appropriate circuits available in a library and generating the corresponding sizing rules.>