Our rebuttal statement is in two parts. A. Generic rebuttal: the area of scheduling is very active with more than 3,000 papers published over this decade alone in good journals. In addition, Krishna and Shin note, in 1997 itself, that the number of papers in the area seems to have increased exponentially since 1970. As a consequence, it is rather difficult to get a handle on all of them.. The records indicate that several aspects of our work appear to be very contemporary to the works of some of the other's work cited by the author. This goes to show that more than one person can have the similar approach to solving similar problems. B. Technical rebuttal: the work quoted by Sohn et al. (1998) deals with the analysis of heterogeneous CPUs. In particular, with the analysis of minimizing the cost (as in $) by selecting the lowest selection of CPUs available that will finish a job in a given time frame. They also analyze the minimum time as well for a given selection of CPUs. Their timeline shows all processes finishing at the same time and does not take into account applications that transfer result data, which our paper does.

This paper considers an analytic data distribution for improving the performance of host-client type parallel applications which exhibit serialized communication patterns. The technique involves assuming the serialized communications is enforced, which simplifies data analysis and can provide the basis for real-time dynamic load balancing. This distribution has been tested using a parallel matrix multiplication implementation and a parallel MPEG compression implementation. The key results of this paper are that analytic distribution can reduce execution time and increase scalability of certain parallel applications over typical equal data distributions.

Presents the design of the software system ADTEST (ADa TESTing), for generating test data for programs developed in Ada83. The key feature of this system is that the problem of test data generation is treated entirely as a numerical optimization problem and, as a consequence, this method does not suffer from the difficulties commonly found in symbolic execution systems, such as those associated with input variable-dependent loops, array references and module calls. Instead, program instrumentation is used to solve a set of path constraints without explicitly knowing their form. The system supports not only the generation of integer and real data types, but also non-numerical discrete types such as characters and enumerated types. The system has been tested on large Ada programs (60,000 lines of code) and found to reduce the effort required to test programs as well as providing an increase in test coverage.

Free text database searching is a natural candidate for acceleration by run time reconfigurable custom computing machines. We describe a fully pipelined search machine architecture for scoring the relevance of textual documents against approximately 100 relevant target words, with provision for limited regular expression matching and error tolerance. An implementation on the SPACE custom computing platform indicates that throughput in the order of 20 megabytes per second is achievable on ALgotronix FPGAs if a locally synchronous design style is adopted and global communications minimized. Partial reconfiguration of the datapath at run time, in around 3 seconds, serves to maximize the density of data storage on the machine and correspondingly avoid costly input from the environment.

The implementation of three parallel sorting algorithms, namely binary sort, odd-even transposition sort and bitonic sort, on a network of transputers is analysed in the paper. The variation in the performance of these algorithms as the number of processors and sort size are changed is investigated. Experimental results show that when up to eight transputers are used, connected as a linear pipeline configuration, all three algorithms can achieve reasonable speedup ratios. The bitonic sort, binary sort odd-even transposition sort achieve speedup ratios of 5, 4.4 and 4, respectively, when eight processors are used to sort 100,000 integers. Analytical models are derived which can be used to predict the performance of the three algorithms when a linear pipeline configuration is used. The predicted performance of the algorithms is compared with the experimental performance in order to validate the model. When the models are used to predict the performance using 16 transputers, it is found that the speedup does not significantly improve compared to the performance achieved with eight transputers. This shows that interprocessor communication has a significant effect on the algorithmic performance when a larger number of processors are used. The conclusions reinforce the fact that the binary and bitonic sorting algorithms are not well-suited to a linear pipeline configuration and that they may perform better if a different topology were used, for example a mesh or a cube connection scheme. Further, the analytical technique used for performance modelling as elaborated in the paper can be employed profitably for other multiprocessor systems as well.