This work introduces a pseudo-dynamic design methodology for fully synthesizable standard-cell-based comparators, accompanied by a compact transistor-level model, in subthreshold region, for delay and power estimation. Two non-rail-to-rail input common-mode range (ICMR) topologies, implemented with AOI (and-or-invert) and OAI (or-and-invert) gates, are proposed. Compared with existing dynamic standard-cell-based comparators, the proposed designs achieve higher speed and lower power consumption, while remaining only marginally slower than the best-performing rail-to-rail solution at 150 mV. Post-layout simulations referring to a 45 nm CMOS process for supply voltages of 150 mV and 600 mV demonstrate that the proposed designs offer the best trade-off between delay, power, offset, and noise in ultra-low-voltage scenarios where rail-to-rail operation is not required.

This work presents a novel configurable two-stage inverter-based ultra-low-power (ULP) OTA with digitally adjustable output stage for dynamic adjustments of gain-bandwidth product, (GBW) and average slew rate (${\mathbf {SR}}_{\mathbf {av}}$). This approach improves both the flexibility of the OTA compared to conventional DC-biased designs, providing a reliable solution for mitigating process, voltage, and temperature variations. The circuit is designed using standard cells in a 180-nm CMOS process and is then fully synthesizable. Experimental measurements are executed over process corners and voltage variations. The proposed OTA works at nominal 0.3-V power-supply voltage and consumes only 1.2 nW, while exhibiting 56-dB DC gain and 7.6-kHz maximum GBW with 5-pF capacitive load.

Roughly a quarter of patients affected by epilepsy experience drug-resistant seizures, which cannot be treated with pharmacological therapy. For these individuals, implanted neurostimulation devices, such as the ones used for Deep Brain Stimulation (DBS), have emerged as potentially effective solutions. However, their performance depends heavily on accurate and timely seizure onset identification to trigger the stimulation electrodes. This paper presents a low-complexity automated seizure detection algorithm based on the Teager Energy Operator (TEO), aimed at capturing abrupt power fluctuations in neural signals that precede the ictal state. Unlike traditional machine learning-based approaches, which rely on computationally intensive feature extraction and training processes, the proposed method exploits TEO’s ability to detect instantaneous energy variations, enabling fast and accurate identification of seizures. The algorithm processes multi-channel neural recording data using a lightweight, adaptive thresholding strategy, with an integrated offline calibration process, achieving an accuracy of 99.23% and sensitivity of 96.75% on the clinical CHB-MIT dataset, with an average delay of 2.36 s. A comparative analysis demonstrates that the proposed approach is comparable with several state-of-the-art ML-based solutions in terms of both detection accuracy and latency, while being well-suited for real-time and resource-constrained applications such as implanted neuromodulation systems. To confirm the system’s suitability, the Field-Programmable Gate Array (FPGA) implementation of the proposed architecture demonstrates that the algorithm can be deployed using a relatively small number of hardware resources.

In this work,a novel bulk-driven OTA capable to operate with a supply voltage as low as 400mV is presented. The proposed single stage topology results in an increased differential gain of about 75dB, while guaranteeing a very low power consumption in the range of 1.8nW. The amplifier exploits a body-driven input stage with a current-mirror-based differential to single-ended converter. The gain of the OTA is boosted thanks to the adoption of a cascode configuration and of a positive feedback loop, which allows to increase the output resistance without adding additional current branches. The CMRR is also improved thanks to the adoption of a replica bias loop which takes track of common-mode voltage variations to adjust the common-mode current, resulting in a CMRR higher than 85dB. The circuit has been designed considering a 180nm CMOS technology from TSMC, and post-layout simulations in the Cadence Virtuoso environment have shown an excellent resilience of the proposed OTA to PVT variations.

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with supply voltages as low as 0.3V, maintaining stable power consumption through a reference bias current. The resulting PUF achieves remarkable energy efficiency, consuming only 0.3 fJ per bit, without compromising statistical performance. It exhibits a response bias of 49.42%, a reliability of 99.483%, and a uniqueness of 50.176%. Validation of this novel approach is conducted through simulations and measurements on a 130nm CMOS test-chip, considering a nominal supply voltage of 0.3V, ±10% supply voltage variations, and a temperature range from 0°C to 75°C. Rigorous experimental verification on 20 chip samples, along with detailed explanations of design methodologies, underscores the robustness and practicality of the proposed Body-PUF design. Comparative analyses against state-of-the-art literature reveal that the Body-PUF outperforms previous PUF designs in Figures of Merit (FOM), making it promising for real-world authentication scenarios. Its outstanding trade-off between performance and practicality positions it as a compelling solution for secure applications, including Internet of Things (IoT) devices and other security-critical systems.

This work presents a novel proposal for utilizing the latched ring oscillator (LRO) as a reconfigurable entropy source, outperforming the existing literature on both physical unclonable functions (PUFs) and true random number generators (TRNGs). The PUF working principle and mathematical model are proposed in this manuscript for the first time as well as its performance measured on FPGA. The proposed LRO-based PUF is$2\times $more compact than state-of-the-art PUFs on FPGA. The LRO TRNG architecture has been revisited, and an XOR-tree-based postprocessing technique has been introduced to increase the throughput from 0.76 up to 800 Mbit/s, paving the way for a novel class of high-throughput reconfigurable entropy sources. The results of NIST tests carried out also under supply voltage and temperature variations have demonstrated robust key extraction and secure random number generation for different applications. This comprehensive proposal aims to advance the state of the art in compact and high-throughput entropy sources, catering to the increasing demands of modern cryptographic hardware.

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity trade-off. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.

The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active- RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance and, hence, of the RC time constant. Since S-R circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, we exploit the theory of the adjoint (inter-reciprocal) network in order to develop a detailed model of the cyclostationary noise involved in this kind of circuits. The proposed model allows to gain insight into the different noise sources and transfer functions involved, highlighting the circuit parameters on which the cyclostationary noise depends. Validation of the proposed model has been carried out by comparing analytical results against periodic noise simulations referring to a commercial 130nm CMOS process. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits.

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.

This paper presents a True Random Number Generator (TRNG) exploiting latched-XOR (LX) gates and its implementation on a Xilinx Spartan 6 FPGA device. The proposed LX-TRNG aims at improving the Throughput (TP) of conventional ring oscillators (ROs) based TRNGs by combining the effect of latches metastability and ROs jitter. Measurements results have demonstrated that the generated bitstreams show very good randomness exhibiting a byte (bit) entropy of 7.9979 (0.9997), according to T8-test of AIS-31. The proposed TRNG has also been extensively tested under voltage and temperature variations showing very good robustness. In particular both NIST’s and AIS-31 tests are passed for all the considered supply voltage and temperature ranges. The FPGA implementation occupies only 9 Slices and, despite its compactness, it exhibits a throughput as high as 12.5 Mbit/s with a 50 MHz operating frequency. The computation of the figure of merit$FOM_{E}$has shown the capability of the proposed TRNG to optimize the trade-off between hardware resources, bitstreams entropy and throughput, outperforming previous works.

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110μW thus confirming the advantages of the proposed approach.

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Post layout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design.

The Time Enclosed Logic (TEL) is a dual-rail signaling protocol used in the context of cryptographic circuits in order to maintain the time enclosing of information leakage also in the presence of capacitive mismatch. The capacitive mismatch, due to non-perfectly balanced differential routing, provides additional data-dependent leakage that a malicious adversary could use to recover secret information from a hardware implementation. In this work, a novel TEL-compatible standard-cell based flip-flop for cryptographic application is presented. The new flip-flop is intended to be compatible also for FPGA applications. The novel standard-cell architecture has been tested with energy-defined metrics adopting a 4-bit register as case study, implemented in 40nm CMOS process. It has been found that it is able to reduce the data-dependence of the power consumption up to ×0.05 also in the presence of strong mismatch if compared to unprotected CMOS. A comparison with WDDL and MDPL has shown that NED and NSD are remarkably reduced (up to ×30 and ×40 respectively), and their values are independent from the capacitive mismatch in the novel flip-flop architecture.

In this paper, a novel modeling framework is proposed to quickly estimate the delay variability of logic paths due to random variations, and evaluate the related design margin. The analysis shows that the popular fan-out-of-4 metric F04 can capture the impact of technology and voltage on the delay variations of logic paths. Once those contributions are isolated, the impact of random variations on standard cells' delay is accounted for by means of cell-specific coefficients that are evaluated in a preliminary library characterization phase. The proposed framework is very general and applicable from sub-threshold to nominal voltage, and provides the designer with a deep insight into the main delay variability contributions in a path. It also predicts the impact of design modifications (e.g., logic restructuring, cell up-sizing), and is well suited for pencil-and-paper calculations. Case studies involving three critical paths extracted from designs ranging from microprocessors to specialized hardware show adequate accuracy, with a delay variability error being typically less than 10%.

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies. In order to further demonstrate the advantages of the proposed topology, it has also been used to design a D flip-flop (DFF), where thanks to the feature to need just 1 clock differential pair; a further speed improvement is achieved over the conventional triple-tail topology. Indeed, by comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF, a 54% improvement in the maximum operating frequency is found when using the proposed folded DFF.

We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed-loop bandwidth decreased to 33 MHz when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, while the other main opamp performance parameters remain almost unchanged compared to the standard solution.

The main drawback of current-mode interface circuits for on-chip capacitive sensors is that the measurement sensitivity is adversely affected by the sensor parasitic capacitance. This causes a strong limitation in the range of applicability of CM interfaces. In this paper we propose a technique that avoids this problem and allows the design of high-performance CMOS interfaces. The proposed solution is based on a feedback loop that, during an autotuning phase, sets the driving current level, hence ensuring virtually the same accuracy irrespectively of the parasitic capacitance. The technique was implemented and designed using a 65-nm CMOS technology. Simulation results are found in close agreement with those theoretically expected, resulting also in an increased accuracy of the capacitive variation detection.

In this paper, the effectiveness of the recently proposed Leakage Power Analysis (LPA) attacks to cryptographic circuits is analyzed in the presence of process variations. Reference circuits (e.g., S-BOX, crypto core) were designed in various logic styles, and their robustness against LPA attacks was comparatively evaluated through Monte Carlo simulations in 65 nm. Analysis allowed for better understanding the impact that process variations have on the outcome of LPA attacks, which is an aspect that is not understood currently. Results show that LPA attacks are rather effective also under die-to-die and within-die process variations. Moreover, the comparison between different logic styles showed that standard CMOS logic circuits are extremely vulnerable to LPA attacks. Other logic styles that are robust against traditional Differential Power Analysis (DPA) attacks were also compared. Interestingly, analysis showed that these logic styles are still vulnerable to LPA attacks. Hence, LPA attacks are an even greater threat to Smart Cards information security, compared to DPA attacks. Moreover, traditional methods to protect Smart Cards against DPA attacks are ineffective in counteracting LPA attacks, thereby showing that a significant research effort will be needed to counteract LPA attacks with suitable solutions that ensure high security standards.

This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.

A cascode current mirror with auxiliary body-driven feedback loop is proposed. Main performance parameters are analytically evaluated and compared to those of a conventional high-swing cascode and of a recently-proposed body-driven topology. Simulations are also provided confirming improvements in the achievable output resistance (important for short channel technologies), DC accuracy, and input dynamic range. Linearity, bandwidth, noise and voltage requirements are substantially the same of the conventional high-swing cascode solution.

In this paper we consider a side-channel attack on a chaos-based random number generator (RNG) based on power consumption analysis. The aim of this attack is to verify if it is possible to retrieve information regarding the internal state of the chaotic system used to generate the random bits. In fact, one of the most common arguments against this kind of RNGs is that, due to the deterministic nature of the chaotic circuit on which they rely, the system cannot be truly unpredictable. Here we analyze the power consumption profile of a chaos-based RNG prototype we designed in 0.35 mum CMOS technology, showing that for the proposed circuit the internal state (and therefore the future evolution) of the system cannot be determined with a side-channel attack based on a power analysis. This property makes the proposed RNG perfectly suitable for high-security cryptographic applications.

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential pair cannot be used. An example implementation in a 65-nm CMOS technology, using plusmn0.35 V supply voltage and a simple 6-transistor CCH topology, shows a 15.5-dB gain enhancement with a good robustness against process variations.

In CMOS smart sensors and microsystems it can be very convenient to integrate both analog and digital circuits in the same chip; since the supply voltage for high-accuracy, high- precision interfaces should be as immune from disturbances as possible, low drop out regulators are often necessary. Here we show a CMOS, dual op amp, fast, low drop out regulator which allows to diminish the power supply gain by orders of magnitude up to very high frequencies.

Temperature measurement is becoming increasingly important in integrated circuits and microsystems; nevertheless, existing techniques for the integration of high accuracy, high precision temperature sensors are not optimal for deep sub-micron CMOS processes. Here we describe a low voltage, low power, compact, high accuracy, high precision temperature sensor for deep sub-micron CMOS systems; our approach takes advantage of charge balancing and charge sharing for low current consumption, does not use resistors for compactness, and takes advantage of both PTAT and autozero techniques for high accuracy and high precision; the circuit can be operated at low supply voltages. As a proof of concept, we report transistor level simulations in a standard 0.13 mum process; the sensor only sinks about 6 muA from a 1.2 V supply voltage, achieving a power dissipation as low as 7.2 muW.

We present a flexible mixed-signal architecture for the synthesis of an n-port analog network. It exploits a field programmable gate array as digital processing element and second generation current conveyors as analog input/output blocks. To validate the approach, a prototype is realized for the basic case of a two-port network and experimental results in agreement with those expected are provided.

New complex tissue microstructure estimators have been presented recently in order to elucidate white matter fibre orientations. Since these algorithms are based on the diffusion-weighted signal profile, the estimations are affected by noise artefacts. The proven robustness of these methods cannot counteract distortions since the statistical Rician behavior has not been taken into account. In this study, two techniques to counteract the noise distortions are presented to improve the fibre orientation estimations. Simulations and in vivo experiments show an improvement in the angular resolution and convergence of the results. One of these strategies represents a good compromise between computational cost and result improvements.

A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.

We describe the first ever reported continuous time, gain enhanced voltage amplifiers which are almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35μm CMOS process; Monte Carlo simulations demonstrate both a significant gain enhancement and its robustness against spread of process parameters.

The authors describe low voltage current and voltage references which only use MOSFETs in strong inversion and pnp substrate transistors; both the references exhibit very good performance in terms of power supply rejection and do not require compensation capacitances; the minimum supply voltage is about 0.8V for the current reference and 1.2V for the voltage reference.

We propose a linearization technique, for CMOS differential pairs employing resistive source degeneration, which exploits the bulks of the pair as additional control terminals. Simulations were performed using a 0.25-μm process, on an example design powered with 2.5V and 1 mA. Compared to the traditional source-degenerated transconductor, the proposed approach allows a THD reduction in the voltage-to-current conversion by 10dB, for an input differential signal of 0.5Vppand for frequencies up to 100MHz.

A CMOS high-linearity transconductor useful for IC filtering applications is presented. It is based on a feedback unity-gain amplifier driving a resistor to achieve linear voltage-to-current conversion. Simulation results are provided on a design example using a 0.35-mum technology, powered from a 3.3V supply, and using a total dc current of 150 muA. The 3-dB bandwidth was 630 MHz and HD3, onto a load resistor of 20kOmega, was -82 dB at 1MHz.

The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result a SCARD chip designed by using the developed design flow is currently implemented

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

A novel current measuring technique is introduced which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported and the achievable advantage in terms of sensitivity is discussed too

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-mum CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-/spl mu/m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.