EDBT 2026 Demo / reviewers in the wild / expert
Satoshi Nakano
dblp:40/6551
· DBLP profile ↗
7ranked-venue papers
1as first author
4since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 since 2021Artificial intelligence and machine learning · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Stable Haptic Shared Autonomy for Wall Landing of Two-Wheeled Drones via Control Barrier FunctionsabstractThis paper presents a novel control method using Haptic Shared Autonomy (HSA) for two-wheeled drones that can drive on surfaces and fly in the air. These drones can switch between flight and contact-based locomotion, enabling versatile operation in complex environments, but tend to become unstable when transitioning from flight to wall-running mode due to wall-collision impacts. To address this, we formulate a human-in-the-loop framework in which the operator inputs commands and receives haptic feedback via a haptic device. We design Control Barrier Functions (CBFs) and impose an energy-based ℒ2gain constraint to guarantee soft landing. By solving a Sequential Control Force (SCF) problem, we compute the drone’s control inputs and haptic feedback forces, automatically adjusting the approach speed. Simulations demonstrate that the proposed method achieves effective soft wall landings while preserving the human operator’s intent. Seri Tanaka, Satoshi Nakano, Gennaro Notomista, Manabu Yamada |
IECON | 2 |
| 2023 | Disturbance Rejection Using the Combination of Equivalent-Input-Disturbance and Model-Predictive-Control MethodsabstractThis paper presents a new equivalent-input-disturbance (EID) approach that is the combination of the EID approach and model-predictive-control (MPC) method. The EID approach estimates the influence of a disturbance and uses it to reject the disturbance. Thus, the amplitude of the control input can be beyond the limitation if the original disturbance is large. To solve this problem, this paper combines the EID approach and the MPC method. The MPC method adjusts the amplitude of an estimated EID during a large disturbance. A numerical example uses a structural model and an earthquake. The results of it verify the validity of our method and the presented method has a better control performance than the previous EID approach. Furthermore, the MPC method adjusts the control input lest it is beyond the limitation. Kou Miyamoto, Yuta Tomiyoshi, Naoto Yoshida, Satoshi Nakano, Jinhua She |
IECON | 4 |
| 2022 | Improving habitability for wind-induced structural vibration by equivalent-input-disturbance approachabstractThis paper improves the habitability of a building for wind load using an equivalent-input-disturbance (EID) approach. In these few decades, many high-rise buildings are constructed around the world. The influence of wind load is large for high-rise buildings, and it causes a decrease in habitability. Habitability relates to the acceleration of a structural response. To improve the habitability of a building for a wind load, we use a lagged-derivative function and EID approach. An EID approach estimates the effect of a disturbance on an output signal. Thus, an acceleration has to be output to estimate an EID. This paper uses a lagged derivative to output the acceleration. The numerical verification uses a building model of 240m and demonstrates that the presented method suppressed the absolute acceleration and improves the habitability of a building to a wind load. Kou Miyamoto, Naoto Yoshida, Yuta Tomiyoshi, Satoshi Nakano, Jinhua She |
IECON | 4 |
| 2021 | Simultaneous robust optimization of tuned mass damper and active control systemabstractThis paper presents a new design method for an active tuned-mass-damper (AMD) system. A tuned-mass-damper (TMD) is one of the common passive-control methods. A TMD reduces a response for resonance frequency. Recently, an AMD, which applies a control engineering for a TMD, is used to increase control performance. Usually, the TMD and the control system of an AMD are designed separately and some nonstructural member or nonlinear characteristics are ignored. This paper presents a simple method that designs both the TMD and the control system of the AMD simultaneously and considers the uncertainties of a structure. The numerical example uses a single-degree-of-freedom model with an AMD and several earthquake waves. The numerical example demonstrates that the presented method suppresses the displacement without increasing absolute acceleration. Kou Miyamoto, Satoshi Nakano, Jinhua She, Daiki Sato, Yinli Chen |
IECON | 2 |
| 2015 | Three-MLP Ensemble Re-RX algorithm and recent classifiers for credit-risk evaluationabstractCredit-risk evaluation is a challenging and important task in the domain of financial analysis for which many classification methods have been suggested. In this paper, we present the results for eight real-life credit-risk two-class mixed datasets (i.e., discrete and continuous attributes) analyzed by the Three-MLP Ensemble Re-RX algorithm (shortened to “Three-MLP Ensemble”). Clarifying the neural network decisions by explanatory rules that capture the learned knowledge embedded in the networks can help a credit-risk manager explain why a particular applicant is classified as either bad or good. To compare the Three-MLP Ensemble performance, we executed comprehensive rule extraction experiments on eight two-class mixed datasets commonly used for benchmarking studies in credit-risk evaluation. The extremely high accuracy of the Three-MLP Ensemble outperformed the accuracies by the Re-RX algorithm and a variant. In this study, we also compared the accuracy of the Three-MLP Ensemble with that of classifiers recently proposed. It is concluded that neural network rule extraction by the Three-MLP Ensemble is a powerful management tool that allows us to build advanced, comprehensible, and accurate decision-support systems for credit-risk evaluation. Yoichi Hayashi, Shonosuke Yukita, Satoshi Nakano, Guido Bologna |
IJCNN | 4 |
| 2012 | Mobile-Carrier Churning Behavior Modeling Based on Customer SatisfactionabstractThe Japanese mobile phone market is in the matured stage. Under competitive conditions, the most important objective of a mobile-carrier is to increase the market share. The aim of this research is to understand mobile-carrier choice behavior under assumed market conditions. We propose the binary choice models of which alternatives are change to other carrier or not. Three models are constructed based on survey data for three mobile-carriers: NTT docomo, au by KDDI, and Soft Bank. Each model has eight factors expressed by the satisfaction levels for mobile-service characteristics. It is shown that important decision-making factors vary from carrier to carrier. It implies that a mobile carrier should keep and improve the satisfaction level of the important factors in order to increase the market share. Satoshi Nakano, Akiya Inoue, Kiyotaka Otsuka, Takeshi Kurosawa, Motoi Iwashita, Ken Nishimatsu |
SNPD | 1 |
| 2012 | Verification work reduction methodology in low-power chip implementationabstractIn order to achieve satisfactory verification for complicated low-power demands in green products, we propose a verification work reduction methodology. It consists of three step, namely virtual, direct actual, and actual model simulations. Virtual low-power simulation inserts low-power cells, such as isolators or level shifters, virtually and simulates logical behavior for design under test (DUT) based on user-defined power mode. Direct actual low-power simulation replaces behavior models without non-logical pins for some of modules with actual models with non-logical pins, which are Vdd and Gnd, and simulates DUT in mixed level. Actual low-power simulation simulates DUT by using actual models with non-logical pins for all cells and hard macros. We introduce techniques which classify the type of the bugs on which we focus at each verification step and prevent the concerned bugs from leaking to the latter verification step as much as possible. We applied our methodology to an actual chip and could reduce the total simulation period until tape-out by 38.8% and the total chip development period by 10%, compared with the conventional methodology. Masanori Kurimoto, Takeshi Yamamoto, Satoshi Nakano, Atsuto Hanami, Hiroyuki Kondo |
ACM Trans. Design Autom. Electr. Syst. | 3 |