Demo Data from EDBT 2026 / reviewers in the wild / expert
Fayez El Guibali
dblp:40/6553
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 67% Performance modeling and evaluation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › arbitration
bus arbitration |
0.0 | 1 | 1989 | Design and Analysis of Arbitration Protocols · IEEE Trans. Computers 1989 |
Interconnection networks and networks-on-chip
multiprocessor interconnection |
0.0 | 1 | 1989 | Design and Analysis of Arbitration Protocols · IEEE Trans. Computers 1989 |
Performance modeling and evaluation
queueing models |
0.0 | 1 | 1989 | Design and Analysis of Arbitration Protocols · IEEE Trans. Computers 1989 |
Methods — techniques the papers use, named apart from their topics
markov modeling · 0.0hardware implementation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Design and Analysis of Arbitration ProtocolsabstractArbitration protocols are needed to prevent conflicts when several processors share a common resource. Five arbitration protocols, commonly used in digital systems, are modeled and their hardware implementations are discussed. The effect of the chosen protocol on the performance of the system, access time (delay before the bus is available) and data throughput (channel utilization efficiency) for each processor, can be studied using the models for these protocols. Four of the protocols considered are identified as being suitable for multiprocessor systems. It is shown that the rotating-priority protocol gives the best system performance. The fifth protocol, the unequal-priority protocol, is shown to offer the worst performance. This is because the protocol was originally intended for single-processor systems. Hardware schemes for the other four protocols are proposed. The schemes are decentralized and require a smaller number of communication lines between the processors. Live insertion and removal of processors from the system is possible since bus-status information is available to all processors at all times.> Fayez El Guibali |
IEEE Trans. Computers | 1 |