This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.

This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm2 in a 6-metal 0.18m CMOS process. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core [1].

This paper introduces novel transistor reordering schemes to reduce the expected or average dynamic power dissipation in CMOS circuits. The transistor reordering is based on the signal probability values at the inputs of the gates. The paper begins with a simple analytical model for the dynamic power dissipation in a static NAND gate. The model is used to derive an algorithm for transistor reordering which reduces dynamic power dissipation. A simulation technique for accurately measuring the power dissipation in NAND gates is also presented, along with the results of the reordering algorithm. A transistor reordering algorithm for CMOS complex gates is subsequently presented. Transistor reordering is found to be an effective way to reduce power dissipation in all of these circuits, with the reduction in dynamic power dissipation compared to the worst case configuration, being as high as 50% in some instances. The limited overhead associated with transistor reordering encourage its application as a low power design technique.

We propose a new frequency hop code, called the extended hyperbolic congruential (EHC) code. The properties of the code, determined via hit array analysis, indicate almost ideal cross- and auto-ambiguity characteristics. Furthermore, the code can be defined recursively, enabling a simple hardware implementation. This makes the code attractive for code division multiple access (CDMA) communication systems.

In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates.>

In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.>