In this paper, an 8 bit 500 MSPS Flash ADC has been presented which incorporates a ramp signal based offset compensation technique. The comparator used in the flash ADC is of Threshold-Inverter-Quantization (TIQ) concept. For TIQ-based comparators, the offset voltage is a function of the individual threshold voltages of the NMOS and PMOS transistors, voltage supply variation and aspect ratios of the transistors. In this work, a 180-nm CMOS process technology has been used to implement the comparator circuits. Monte-Carlo analysis of the TIQ-based comparators show a$3-\sigma$variation of 6.79 mV, which equates to a value of 3 LSB for the ADC, having a dynamic range of 500 mV. In order to compensate the offset voltage, a ramp signal is used at a sampling speed of 10 MHz. Cumulative values of the thermometric codes thus generated are compared with ideal values to perform the compensation procedure. With$\pm 3$LSB random offset of all the comparators, the ADC provides an ENOB of 5.139 bits. Post compensation, the ENOB improves to 7.73 bits.

This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18-$\mu \text{m}$CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration.

This paper proposes a foreground calibration technique of a pipeline ADC, using a mixed signal back-end calibration circuit. This calibration circuit contains only a digital comparator and a 1storder low pass filter (LPF). At the front end analog part, a variable gain amplifier (VGA) responds to the back-end unit to calibrate a pipeline stage gain. Unlike typical radix extraction principle of a background or foreground calibration technique, the proposed technique forces the gain of the multiplying-DAC (MDAC) of a 1.5-bit target stage to 2 V/V. To achieve this, the sampling capacitor ( CS) and the feedback capacitor ( CF) of the said stage are ratio-ed with a skew of > 2. In order to compensate the skew, a gain controllable VGA is tuned to such a gain so that overall gain of the MDAC becomes exactly equal to 2 V/V or the ideal gain. In this paper, an 11-bit pipeline ADC has been simulated which contains a 1.5-bit non-ideal pipeline stage followed by a 10-bit back-end ADC (BE-ADC). Simulations have been performed to compare the linearity of the ADC at different gain value of the VGA. With an initial VGA gain value of 15 V/V and 35 V/V, the calibration algorithm iterates to final value of VGA gain of A=24.55 V/V, when the calibration loop breaks. Behavioural simulation of this 11-bit pipeline ADC shows that at Nyquist rate, after calibration, SNDR, SFDR and ENOB are 64.73 dB, 74.02 dB and 10.46 bits respectively.

The paper presents a novel digital foreground calibration algorithm of a pipeline ADC. Unlike many of the contemporary digital calibration algorithms, which use least mean square (LMS) based iterative method of radix extraction, the proposed algorithm extracts the radix using a simple time-average determination of the radices. In this paper a 10-bit pipeline ADC has been implemented with two non-ideal 1.5-bit MSB stages. The back-end ADC (BE-ADC) contains 6 1.5-bit stages followed by a 2-bit flash stage. Since the radices of the first two stages equate to their multiplying-digital-to-analog-converter (MDAC) gains, determination of the radices helps to linearize the ADC output. Although the proposed calibration algorithm is capable of extracting the radices of all the stages, as an illustration only two stage calibration process has been presented in this paper. Simulation results of a 10-bit pipeline ADC sampling an input signal at approximately Nyquist rate show before calibration the ADC produces a signal-to-noise-and-distortion-ratio (SNDR) of 35.42 dB and spurious-free-dynamic-range (SFDR) of 42.16 dB. After applying the calibration, SNDR and SFDR improves to 56.89 dB and 61.37 dB respectively.

This paper describes a new radix based calibration technique for pipelined analog-to-digital converters (ADCs). The proposed technique uses sinusoidal signal sampled at Nyquist rate to mitigate the effects of capacitor mismatch and finite op amp gain error that degrade the performance of a typical pipelined ADC. The calibration has been illustrated using a 1.5-bit per stage non-flipover topology. This technique is promising compared to the existing foreground calibration algorithms as it requires sinusoidal input which is easily available. Since this technique does the calibration at Nyquist rate it captures the finite op amp settling effect, which no other foreground calibration technique does. Behavioral simulations for a 12-bit pipelined ADC which has 11, 1.5-bit stages followed by 2-bit flash, validate the calibration technique.