Samin Sohrabi

dblp:400/2117 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Memory systems · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
edge accelerator
0.912025
ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI · DAC 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI · DAC 2025
Memory systems › processing-in-memory
near-data processing
0.312025
ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI · DAC 2025
Memory systems
processing-in-memory
0.312025
ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI · DAC 2025

Methods — techniques the papers use, named apart from their topics

residue number system · 0.9SOT-MRAM · 0.9
YearPublicationVenuePosition
2025 ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI
abstract
This paper presents ResISC, an RNS-based integrated sensing and computing architecture enabling efficient edge AI. ResISC platform features (i) an in-sensor residue encoder converting images directly to RNS in the analog domain, (ii) an energy-efficient RNS-based processing-near-sensor CNN accelerator utilizing SOT-MRAM, and (iii) an innovative mixed-radix unit for efficient activation operations. By employing selective channel deactivation, ResISC reduces computation overhead by up to $89 \%$, while achieving a $3.4 \times$ improvement in power efficiency and up to a $71 \times$ reduction in execution time compared to processing-in-MRAM platforms. Experiments on various datasets demonstrate that ResISC achieves competitive accuracy levels (up to $94.63 \%$ on CIFAR-10) with minimal degradation, making it an ideal solution for power-constrained, real-time edge applications.
Sepehr Tabrizchi, Samin Sohrabi, Mohamadreza Mohammadi, Ramtin Zand, Shaahin Angizi, Arman Roohi
DAC2