Demo Data from EDBT 2026 / reviewers in the wild / expert
Joonsik Yoon
dblp:401/8269
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 77% Memory systems · 23% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › memory repair
built-in self-repair |
0.9 | 1 | 2025 | A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Memory systems › DRAM › DRAM architecture
high bandwidth memory |
0.9 | 1 | 2025 | A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Hardware reliability and fault tolerance
memory reliability |
0.9 | 1 | 2025 | A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Hardware reliability and fault tolerance › redundancy
redundancy analysis |
0.9 | 1 | 2025 | A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Methods — techniques the papers use, named apart from their topics
redundancy analysis algorithm · 0.9content-addressable memory · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | VocalAgent: Large Language Models for Vocal Health Diagnostics with Safety-Aware EvaluationabstractVocal health plays a crucial role in peoples' lives, significantly impacting their communicative abilities and interactions. However, despite the global prevalence of voice disorders, many lack access to convenient diagnosis and treatment. This paper introduces VocalAgent, an audio large language model (LLM) to address these challenges through vocal health diagnosis. We leverage Qwen-Audio-Chat fine-tuned on three datasets collected in-situ from hospital patients, and present a multifaceted evaluation framework encompassing a safety assessment to mitigate diagnostic biases, cross-lingual performance analysis, and modality ablation studies. VocalAgent demonstrates superior accuracy on voice disorder classification compared to state-of-the-art baselines. Its LLM-based method offers a scalable solution for broader adoption of health diagnostics, while underscoring the importance of ethical and technical validation. Yubin Kim 0002, Taehan Kim, Wonjune Kang, Eugene Park, Joonsik Yoon, Xin Liu 0034, Daniel McDuff, Hyeonhoon Lee, Cynthia Breazeal, Hae Won Park 0001 |
INTERSPEECH | 5 |
| 2025 | A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBMabstractHigh bandwidth memory (HBM) represents a significant advancement in memory technology, requiring quick and accurate data processing. Built-in self-repair (BISR) is crucial for ensuring high-capacity and reliable memories, as it automatically detects and repairs faults within memory systems, preventing data loss and enhancing overall memory reliability. The proposed BISR aims to enhance the repair rate and reliability by using a content-addressable memory structure that operates effectively in both offline and online modes. Furthermore, a new redundancy analysis algorithm reduces both analysis time and area overhead by converting fault information into a matrix format and focusing on fault-free areas for each repair solution. Experimental results demonstrate that the proposed BISR improves repair rates and derives a final repair solution immediately after the test sequences are completed. Moreover, hardware comparisons have shown that the proposed approach reduces the area overhead as memory size increases. Consequently, the proposed BISR enhances the overall performance of BISR and the reliability of HBM. Joonsik Yoon, Hayoung Lee, Youngki Moon, Seung Ho Shin, Sungho Kang 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |