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Yanliang Sha

dblp:401/8305 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0008-8878-1695ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
signal integrity
0.912025
LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Integrated circuit design › interconnect
high-speed serial link
0.312025
LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

non-autoregressive transformer · 0.9artificial neural network · 0.9
YearPublicationVenuePosition
2025 LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer
abstract
High-speed serial links are essential for low-latency, high-bandwidth communication in data-intensive systems. Signal integrity (SI) of transmitters (TXs) directly impacts transmission quality of the links, while TXs' delay also introduces timing mismatches that degrade link integrity. In this paper, we propose LiTformer, a Transformer-based model for efficient SI analysis of high-speed link TXs, featuring a non-sequential encoder and a multi-head Transformer decoder to incorporate link parameters and capture long-range dependencies. By adopting a nonautoregressive approach, it enables parallel sequence prediction. We also introduce an ANN-based delay model for fast TX delay estimation. Considering link factors including crosstalk in multiple-link systems, LiTformer enables accurate and fast long-sequence signal prediction at high data rates, achieving efficient SI analysis for TXs. Experimental results show LiTformer achieves 437-996 × speedup in eye diagram prediction over SPICE, with mean errors of 0.15-1.57%. It supports 4-bit signals at Gbps data rates for single-ended and differential TXs, including NRZ and PAM4 formats. The delay model predicts TX delay achieving a speedup of four orders of magnitude with errors of 0.86-2.69%.
Songyu Sun, Yanliang Sha, Qi Sun 0002, Quan Chen 0007, Zhou Jin 0001, Cheng Zhuo
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2024 LiTformer: Efficient Modeling and Analysis of High-Speed Link Transmitters Using Non-Autoregressive Transformer
abstract
High-speed serial links are fundamental to energy-efficient and high-performance computing systems such as artificial intelligence, 5G mobile and automotive, enabling low-latency and high-bandwidth communication. Transmitters (TXs) within these links are key to signal quality, while their modeling presents challenges due to nonlinear behavior and dynamic interactions with links. In this paper, we propose LiTformer: a Transformer-based model for high-speed link TXs, with a non-sequential encoder and a Transformer decoder to incorporate link parameters and capture long-range dependencies of output signals. We employ a non-autoregressive mechanism in model training and inference for parallel prediction of the signal sequence. LiTformer achieves precise TX modeling considering link impacts including crosstalk from multiple links, and provides fast prediction for various long-sequence signals with high data rates. Experimental results show that LiTformer achieves 148--456× speedup for 2-link TXs and 404--944× speedup for 16-link with mean relative errors of 0.68--1.25%, supporting 4-bit signals at Gbps data rates of single-ended and differential TXs, as well as PAM4 TXs.
Songyu Sun, Yanliang Sha, Quan Chen 0007, Cheng Zhuo
ICCAD3