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Linrui Jiang

dblp:402/3612 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Reconfigurable computing and FPGAs · 23%
Computer graphics and multimedia
1 paper
Rendering · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Rendering
neural rendering
0.912025
Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers · HPCA 2025
Hardware accelerators and domain-specific architectures
neural rendering accelerator
0.912025
Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers · HPCA 2025
Reconfigurable computing and FPGAs
reconfigurable architecture
0.312025
Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers · HPCA 2025

Methods — techniques the papers use, named apart from their topics

dataflow reconfiguration · 1.7benchmarking · 1.7
YearPublicationVenuePosition
2025 Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers
abstract
Recent advancements in neural rendering technologies and their supporting devices have paved the way for immersive 3D experiences, significantly transforming human interaction with intelligent devices across diverse applications. However, achieving the desired real-time rendering speeds for immersive interactions is still hindered by (1) the lack of a universal algorithmic solution for different application scenarios and (2) the dedication of existing devices or accelerators to merely specific rendering pipelines. To overcome this challenge, we have developed a unified neural rendering accelerator that caters to a wide array of typical neural rendering pipelines, enabling real-time and on-device rendering across different applications while maintaining both efficiency and compatibility. Our accelerator design is based on the insight that, although neural rendering pipelines vary and their algorithm designs are continually evolving, they typically share common operators, predominantly executing similar workloads. Building on this insight, we propose a reconfigurable hardware architecture that can dynamically adjust dataflow to align with specific rendering metric requirements for diverse applications, effectively supporting both typical and the latest hybrid rendering pipelines. Benchmarking experiments and ablation studies on both synthetic and real-world scenes demonstrate the effectiveness of the proposed accelerator. It achieves real-time rendering speeds (> 30 FPS) and up to $119 \times$ speedups over state-of-the-art neural rendering hardware across varied rendering pipelines, while adhering to power consumption constraints of around 5 W, typical for edge devices. Consequently, the proposed unified accelerator stands out as the first solution capable of achieving real-time neural rendering across varied representative pipelines on edge devices, potentially paving the way for the next generation of neural graphics applications.
Chaojian Li, Sixu Li, Linrui Jiang, Jingqun Zhang, Yingyan (Celine) Lin
HPCA3