Abstract The globalization of the integrated circuit design industry makes it easier for the adversary to pirate intellectual property and insert hardware Trojans (HTs). Although many HT protection methods have been proposed, some malicious elements can still be inserted into vulnerable nodes. Trojans are usually inserted in the rare nodes with the lowest observability, which makes it hard for testers to discover them. In this paper, we propose a dual-protection technology to protect the circuit against HT attacks based on observability. First, we propose an algorithm to increase the low observabilities of the circuit, so as to make it difficult for attackers to implant HTs. Several existing approaches try to identify the low observability by setting a threshold artificially, which is not generic. We do not need to set thresholds when targeting the low observability. Second, we present another logic locking algorithm to enhance the entire circuit’s security further. Simulation results on ISCAS85 benchmark and several larger circuits show that the proposed HT protection method has increased the lowest observability of the circuit by an average of 370.76 times. Furthermore, the logic locking technique maximizes the ambiguity for an attacker. Compared with the state of the art, the proposed logic locking can obtain better results, achieving a Hamming distance that is closer to 50% between the correct and incorrect outputs when a wrong key is applied.

Traditional logic synthesis methods are based on Boolean logic, which tends to produce redundant logic structures in dense circuit applications, such as complex number operations and error detection/correction coding. Traditional Boolean and Reed-Muller (TB-RM) logic synthesis method combining traditional Boolean (TB) logic and Reed-Muller (RM) logic can improve comprehensive optimization indexes and reduce cost. The existing TB design method is not effective when dealing with constrained systems with high-resource utilization requirements. In addition, traditional synthesis methods do not consider multiobjective optimization of area, power consumption and reliability. To solve these problems, we propose an effective dual logic synthesis method (EDSM), which includes dual logic detection method (DDM) and differential evolution algorithm based on multidimensional mutation strategy (DE-MMS). DDM can complete the logic detection function, and DE-MMS can further optimize the polarity. In addition, to evaluate the soft errors occurring more efficiently at the logic level, we propose a soft error rate (SER) estimation model. Experimental results show that compared with state-of-the-art evolutionary algorithms, EDSM can search for optimal solutions in all optimization problems; compared with commonly used TB-based minimization methods, EDSM has obvious advantages in multiobjective optimization of area, power consumption and SER. After 6-LUT FPGA technology and standard cells mapping, by selecting area as the optimal cost implementation, we obtain average improvements in the area of 14% and 2%, respectively.

The globalization of the IC supply chain has increased the possibility for adversaries to insert hardware Trojans (HTs), which are always inserted into nodes with high concealment. Although several methods have been introduced to detect HTs, they do not specifically focus on node concealment and are not accurate enough. In this paper, 11 new features are proposed reflecting the node concealment, i.e, the controllable difficulty and observable difficulty of nodes, for machine-learning-based HT detection. The proposed features comprehensively consider the circuit structure information and signal propagation characteristics, and quantify the possibility of attacks. After combining the proposed features with existing ones for classification, the true positive rate (TPR) is 35 points higher than that without using the proposed features. Compared with the state-of-the-art works, our TPR and true negative rate (TNR) have increased by 15.6% and 2.1%, respectively, especially in large-scale circuits. It shows that our method has a great advantage in detection accuracy.

Abstract Security of computer information can be improved with the use of a network intrusion detection system. Since the network environment is becoming more complex, more and more new methods of attacking the network have emerged, making the original intrusion detection methods ineffective. Increased network activity also causes intrusion detection systems to identify errors more frequently. We suggest a new intrusion detection technique in this research that combines a Convolutional Neural Network (CNN) model with a Bi-directional Long Short-term Memory Network (BiLSTM) model for adding attention mechanisms. We distinguish our model from existing methods in three ways. First, we use the NCR-SMOTE algorithm to resample the dataset. Secondly, we use recursive feature elimination method based on extreme random tree to select features. Thirdly, we improve the profitability and accuracy of predictions by adding attention mechanism to CNN-BiLSTM. This experiment uses UNSW-UB15 dataset composed of real traffic, and the accuracy rate of multi-classification is 84.5$\%$; the accuracy rate of multi-classification in CSE-IC-IDS2018 dataset reached 98.3$\%$.

Approximate arithmetic circuit (AAC) has emerged as a promising high-performance and energy-efficient circuit paradigm, which can be used in many applications with inherent error tolerance. To guarantee the usability of AACs and the availability of resilient applications, it is necessary to analyze the reliability of AACs. Most current literature focus on the error characteristics of AACs and few methods can be applied to estimate the reliability of AACs. These methods mostly have exponential time complexities and evaluate the average reliability assuming the input combinations are equally likely. In reality, the primary input (PI) signals can be given with any probability from 0 to 1. In this article, we assume that the PIs have random signal probabilities and propose approaches to reliability boundary estimation for AACs. First, we propose a new efficient and accurate method to evaluate the reliability of AACs. The method mainly calculates the AAC reliability for an input vector set, and furthermore, during the calculation, the correlation problem is considered to increase accuracy. Then, based upon the proposed AAC reliability evaluation method, we present the approaches to finding the reliability boundary. Randomly given signal probabilities of every PI, two heuristic search algorithms are utilized to find the lowest reliability. A comparison of the results on three series of AACs and the circuits in the EvoApprox8b library confirms that the proposed reliability evaluation method is more accurate and efficient than the previous method. Further experiments verify the plausibility of the calculated reliability boundary of AACs.

Recently, approximate arithmetic circuits (AACs) have been widely used in applications with inherent error tolerance. To guarantee the usability of AACs in the approximation applications, it is necessary to analyze AAC reliability. In this paper, we propose two accurate AAC reliability evaluation methods based on signal reliability analysis, where subtraction correlation coefficient and division correlation coefficient are applied respectively to solve the correlation problem caused by fanout reconvergence. The accuracy and scalability of these two methods are verified by randomly selected circuits from the EvoApprox8b library. The experimental results show that, compared with Monte Carlo (MC) simulation, our two proposed methods have average error rates of 0.34% and 0.65% and the run-time costs are 0.012% and 0.019% of MC’s simulation time. Moreover, the proposed methods are superior to two recently reliability analysis based methods in terms of efficiency and accuracy.

The existing analytical methods for estimation of the reliability of approximate circuits are based on probability transfer module (PTM) method and Monte Carlo (MC) method. However, the PTM-based method is confined to small-scale approximate circuits and large circuits with weak signal correlation, and the MC method is time-consuming to obtain accurate results. This paper presents two methods for reliability estimation of gate-level approximate circuits based on probability gate model (PGM). The first is non-process correlation algorithm that does not consider the correlation among signals to obtain an approximate value of circuit reliability, and its time complexity keeps a linear relation with the number of gates. The second is the processing correlation algorithm which can estimate the correlation caused by fanout nodes of the approximate circuits, and it has the obvious advantage on accuracy, but its time complexity is exponential with the number of fanout nodes in the circuit. Experimental results demonstrate the validity and accuracy of the proposed methods.

Approximate adders have become a focus of approximate circuit design. However, there has been a lack of appropriate methods to evaluate their reliability. The existing analytical methods for accurate circuits cannot be applied to approximate circuits directly, and the Monte-Carlo simulation is time-consuming. Some metrics such as worst-case error, error distance, mean error distance and normalized error distance have been used to describe the reliability characters and arithmetic performance of approximate circuits, but they cannot directly calculate the reliability. This paper presents two methods for approximate adders reliability estimation based on the probabilistic transfer matrix (PTM) model. The first method takes the sum of the probabilities of all acceptable outputs as the probability of acceptable result corresponding to each input. The second method calculates the probability of acceptable result according to the deviation between the acceptable output and exact output. The reliability of approximate adders is calculated by combining the probabilities of the input vectors and those of the corresponding acceptable results. Experimental results demonstrate the validity and accuracy of the proposed methods.