Demo Data from EDBT 2026 / reviewers in the wild / expert
Evangelos Dikopoulos
dblp:402/9157
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
0000-0003-2160-2468ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
in-sensor computing |
0.9 | 1 | 2025 | SEAL: A Single-Event Architecture for In-Sensor Visual Localization · ISCA 2025 |
Methods — techniques the papers use, named apart from their topics
race logic · 0.9analog-to-time conversion · 0.9FPGA prototyping · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | SEAL: A Single-Event Architecture for In-Sensor Visual LocalizationabstractImage sensors have low costs and broad applications, but the large data volume they generate can result in significant energy and latency overheads during data transfer, storage, and processing.This paper explores how shifting from traditional binary encoding to delay-based codes early on can address these inefficiencies, enabling keypoint detection and tracking within digital pixel sensors.The result is SEAL, a Single-Event Architecture for In-Sensor Localization.SEAL optimizes the entire pipeline between the pixel array and the sensor-processor interface by introducing a temporal processor co-designed with analog-to-time converters, followed by a custom heavily quantized frontend processor.Its implementation is fully digital, relying on off-the-shelf CMOS cells and EDA tools, and adheres to race logic's single-wire-per-variable and single-eventper-wire policies to maximize energy and area efficiency wherever possible.Our evaluation-combining analog and digital simulations, FPGA prototyping, and an end-to-end system analysis incorporating a host processor for visual inertial odometry (VIO) backend tasks-demonstrates a 16-61× reduction in the latency of keypoint detection and tracking compared to software baselines running on the host processor, and a 7× reduction in energy consumption compared to a standard digital pixel sensor without processing capabilities.Meanwhile, SEAL preserves robust tracking accuracy: on the EuRoC dataset, the average root mean square absolute trajectory error decreases by 1.0 cm for HybVIO and increases by just 0.3 cm for VINS-Mono compared to their original implementations. Ryan Hou, Thomas Twomey, Vasileios Milionis, Evangelos Dikopoulos, Tianrui Ma, Yuhao Zhu 0001, Georgios Tzimpragos |
ISCA | 4 |