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Youquan Chang

dblp:403/7180 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0008-8719-3197ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › placement › circuit placement
3D IC placement
1.012026
LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › physical design › placement › module placement
macro placement
1.012026
LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
physical design
1.012026
LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › physical design
placement
1.012026
LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

virtual macro insertion · 1.0macro connection reconstruction · 1.0electrostatic field density modeling · 1.0
YearPublicationVenuePosition
2026 LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs
abstract
As integrated circuit design continues to scale, three-dimensional integrated circuit (3D-IC) technology has emerged as a promising solution to extend Moore’s Law. Among various physical design stages, placement plays a pivotal role, directly influencing key power, performance, and area (PPA) metrics. In research that does not consider specific 3DIC process technologies, the state-of-the-art ePlace-3D introduces 3D electrostatic field density modeling, enabling nonlinear placement algorithms to truly address 3D placement problems. However, its complex flow results in low runtime efficiency. In this work, we propose LightPlace, a lightweight and effective 3D placement framework. This framework incorporates Virtual Macro Insertion approach and Macro Connection Reconstruction method, which streamline the macro placement phase and allocate space for subsequent standard cell placement. These innovations enhance runtime efficiency and optimize wirelength. Experimental results on the large-scale Modern Mixed-Size (MMS) benchmarks demonstrate that, LightPlace reduces total wirelength by an average of 10% and achieves up to 4× faster runtime compared to the runtime reported for ePlace-3D.
Chubo Liu, Peiying Lin, Youquan Chang, Zhuo Tang, Kenli Li 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2025 An optimized hierarchical MapReduce framework in supercomputing Internet environment
abstract
Abstract Distributed computing frameworks play a crucial role in supporting compute-intensive applications in the era of big data. The growing demand for computing resources has spurred the interconnection of data centers, leading to the formation of supercomputing Internet. MapReduce is a popular distributed computing framework designed for large independent clusters. The original MapReduce framework deployed on supercomputing Internet performs inefficiently due to redundant geo-distributed reduce operations. Nonetheless, its abstraction remains significant potential. This paper proposes an enhanced MapReduce framework for geo-distributed supercomputing Internet to minimize the necessity for data transmission across data centers. Leveraging hierarchical scheduling techniques, the framework optimizes data locality to mitigate network latency and bandwidth consumption during reduce operations, thereby reducing overall job execution times. The paper introduces a mathematical model for task scheduling within supercomputing Internet and formally describes the data transmission process among data centers. In the job scheduling phase, our framework facilitates efficient overlap of transferring and computing through pre-selected data centers. Meanwhile, in the data transmission phase, the framework aggregate data to reduce the frequency of transmission, thus alleviating the adverse effects on transmission of hierarchical network architecture. Comparative analysis with existing methods demonstrates the efficacy of the proposed framework in addressing similar computational challenges. Empirical evaluations underscore the effectiveness of our method in practice.
Yalin Zhu, Youquan Chang, Jiapeng Zhang 0001, Zhuo Tang
CCF Trans. High Perform. Comput.2