Processing-Near-Memory (PNM) over Compute Express Link (CXL) has strong architectural appeal. However, most existing CXL-attached PNM prototypes remain inflexible or simulation-based and lack integration with full software stacks, which limits their practical deployment. This work introduces CMM-Ax, a deployable hybrid CXL-PNM system that combines streaming near-memory pipelines with device-side programmability and integrates tightly with the Heterogeneous Memory Software Development Kit (HMSDK). Through HMSDK, CMM-Ax exposes CXL-attached memory via standard Linux allocation paths (e.g., malloc and mmap). This allows existing vector databases and search engines to adopt heterogeneous memory with minimal application-level changes, such as selecting the CMM-Ax FAISS backend. CMM-Ax further provides a comprehensive software stack—FAISS integration, a domain-specific compiler for user-defined operators, and a Kubernetes device plugin supporting multi-tenant slicing—capabilities not demonstrated in prior CXL-PNM. Using an FPGA-based CXL Type-3 prototype, CMM-Ax achieves 4.54× higher throughput and 5.56× lower energy per query than a CXL memory-only baseline on the exact k-nearest neighbor (kNN) search. For approximate nearest neighbor (ANN) inverted-file (IVF) workloads, CMM-Ax sustains bandwidth-proportional efficiency at small batches (batch=1: 37% vs. 12% CPU, 7% GPU). In Kubernetes deployments, CMM-Ax–equipped servers can replace a significantly larger CPU-only cluster at equivalent memory capacity and throughput, reducing node count and system energy.

Multiprocessor systems-on-chip (MPSoCs) are evolving toward processor pool-based architecture that employs a hierarchical on-chip network for inter-processor and intra-processor pool communication. This letter presents a systematic exploration method of the cascaded bus matrix-based on-chip network design for processor pool-based MPSoCs. It uses an evolutionary algorithm to find optimal architectures in terms of on-chip area while satisfying a given performance constraint. Since simulation is too time-consuming to evaluate the performance of complex on-chip networks during architecture exploration, we propose to prune the design space efficiently using two novel static analysis techniques: 1) bandwidth analysis considering task execution dependences, and 2) memory contention analysis for accurate performance estimation. Thanks to fast and accurate evaluation by the proposed analysis techniques, we achieved an order of magnitude speed improvement for the architecture exploration without performance loss, compared with a simulation-based approach.

MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP-based MPSoC is extremely wide, application-specific optimization of on-chip communication is a nontrivial task. This paper presents a systematic methodology for on-chip network design of PP-based MPSoC. The proposed approach allows independent configurations of PPs, which leads to efficient solutions than previous work. Since time-consuming simulation is inevitable to evaluate complicated on-chip network during exploration, we do early pruning of design space by a bandwidth analysis technique that considers task execution dependencies. Our approach yields the Pareto-optimal solutions between clock frequency and area requirements. The experiments show that the proposed technique finds more efficient architectures compared with the previous approaches.

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW cosimulation, but also HW-SW codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The PeaCE codesign environment is the first full-fledged HW-SW codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, PeaCE specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the peace codesign environment mainly targeting for multimedia applications with real-time constraints. Peace specifies the system behavior with a heterogeneous composition of three models of computation. The Peace environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique