Demo Data from EDBT 2026 / reviewers in the wild / expert
Nicolás Meseguer
dblp:404/9720
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2026
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU architecture |
1.0 | 1 | 2026 | QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs · HPCA 2026 |
GPUs and heterogeneous computing
GPU computing |
1.0 | 1 | 2026 | QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs · HPCA 2026 |
Compilers and program optimization › parallel program optimization
performance portability |
0.3 | 1 | 2026 | QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs · HPCA 2026 |
Methods — techniques the papers use, named apart from their topics
heuristics · 2.0RISC-V processor · 2.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUsabstractThe growing complexity and parallelism demands of modern GPU workloads have driven architectural innovations toward asynchronous tile transfers (ATTs) to overlap computation and data movement. While ATT units such as the NVIDIA's Tensor Memory Accelerator (TMA) introduce high-throughput memory transfers, programmers must deal with wavefront specialization, select tile sizes, queue slots, and synchronization primitives, all of which are hardware-specific and workloaddependent. Existing GPU libraries fall short-offering limited ATT support and configurability-so developers still resort to manual exploration of this vast parameter space, which is laborious, error-prone, and fundamentally limits performance portability across GPUs. In this work, we present QuCo (Queue Configurator), a single lightweight hardware unit embedded in the GPU that fully automates the ATT configuration process. Inspired by Blackwell GPU design, QuCo includes a compact RISC-V processor, small memory structures for instructions and data, and a GPU Specification Table (GST) storing key architectural parameters. Using the GST and workload characteristics, along with built-in heuristics, QuCo computes optimal queue configurations at kernel launch. This relieves the programmer of the tedious, time-consuming task of tuning and offline profiling, while simultaneously increasing post-compilation performance portability. Nicolás Meseguer, Daoxuan Xu, Yifan Sun 0002, Michael Pellauer, José L. Abellán, Manuel E. Acacio |
HPCA | 1 |