An interleaved converter consists of multiple phases operating out of phase with the well known benefits of reduced input output current and ripples, improved efficiency and better thermal performance. When the interleaved converter is connected to a constant power load, its negative incremental impedance characteristics leads to instability. This leads to an increased oscillation in the DC link voltage and the source current which is interfaced with the interleaved converter. In this manuscript, a robust control consisting of the sliding mode control is proposed to damp the oscillations due to CPL and maintain the DC link voltage and source current within the permissible desired limits. The proposed sliding manifold consists of the power error terms and a voltage error term. The proposed control performance is validated through simulation and experimental results on a 500W three phase interleaved boost feeding a buck converter fed resistive load setup.

This article represents the steady-state analysis and control of a non-ideal single-input/double-output DC/DC converter (SIDOC) named an integrated dual-output converter at continuous conduction mode (CCM). This converter offers positive voltage levels at outputs using a step-up boost converter and a step-down buck converter. This topology is obtained by combining half-bridge pair transistors, a boost converter, and a buck converter. In this way, it has a continuous input current waveform, which is desired for renewable energy systems. This topology is also suitable for residential applications and low-voltage auxiliary power supplies since it obtains multiple voltage levels. To ensure a stable operation, the decoupled-control method is suggested to regulate the output voltages. This method separates the control loops of different output voltages to remove the cross-regulation and cross-coupling of outputs. Then, among available classical compensators, the type-three lead-lag controller is chosen for the compensation. The state-space equations are used to model the converter for non-ideal conditions. Finally, simulations are done using MATLAB/Simulink, which validates the theoretical calculations.

This paper focuses on the reliability studies of the output voltages in a multi-port DC-DC converter called the integrated dual-output converter (IDOC). The Markov process and Bayesian networks (BNs) are used to perform reliability analyses. Bayesian networks (BNs), developed based on machine learning techniques, are suitable for unhiding the dependencies along with estimating the conditional probabilities for reliability studies. The BNLearn and the pgmpy are libraries developed in the Python environment that include the main parts of obtaining a BN: structure learning, parameter learning, and inference. A dataset including the reliability model of each device is created using state sampling and Monte Carlo simulation, considering the open-circuit fault. Next, the hill-climbing (HC) and Bayesian information criterion (BIC) methods are applied to the dataset as searching and scoring functions, respectively, to determine the structure of the BN. Finally, using parameter learning and inference, conditional and joint probability distributions (CPDs and JPDs) are obtained, yielding the reliability of output voltages. Theoretical calculations through the Markov process validate the accuracy of the obtained BN.

The three-level submodule (3L SM) has emerged as a viable alternative to the conventional half-bridge submodule in modular multilevel converters (MMC), primarily due to its reduced footprint. Despite this, there has been no in-depth exploration of MMC topologies utilizing 3L SMs, particularly in the context of motor drive applications. The 3L SM features two capacitors, and the MMC relies on a cascade connection of multiple 3L SMs per phase, necessitating voltage-balancing control for these capacitors. This paper introduces a voltage-balancing control strategy for multiple capacitors, incorporating high-frequency voltage and circulating current injections to ensure optimal performance in low-speed motor drive operations. The voltage commands are normalized and compared with phase-shifted carrier (PSC) PWM triangular waveforms to generate gating signals. The proposed voltage-balancing control method has been validated through a 4160-V/1-MW simulation model using a hardware-in-the-loop (HIL) system.