High-speed SRAM arrays are essential for data-intensive Systems-on-Chip (SoCs). However, accurate timing characterization of these SRAMs requires transistor-level SPICE simulations, which are extremely time-consuming due to the large dimensions and complexity of modern designs. In this work, we present Graph-SRAM, an efficient graph learning-based simulation method using waveform propagation. Our approach models cells and interconnects as heterogeneous graphs and embeds global switching features, enabling a customized Graph Neural Network (GNN) to capture structural and functional patterns in both combinational and sequential circuits. Compared to HSPICE, Graph-SRAM achieves a significant speedup of 6905.32× while maintaining high accuracy, with an average error of only 4.28% in predicting path waveforms.

As technology nodes shrink, static timing analysis (STA) must balance accuracy and efficiency to ensure circuit functionality. Graph-based analysis (GBA) is fast but pessimistic, while path-based analysis (PBA) offers higher accuracy with an expensive runtime cost. However, GBA and PBA rely on lookup table (LUT)-based standard cell libraries, introducing accuracy losses compared to accurate SPICE simulations at advanced technology nodes. This work presents GTN-Path, an efficient post-layout path timing prediction method based on waveform propagation and graph transformer network (GTN). GTN-Path captures structural information to accurately predict waveforms by modeling standard cells and interconnects as graphs. Compared to HSPICE simulations, GTN-Path predicts waveforms with $2.98 \%$ error and delay with $2.96 \%$ error, achieving a speedup of $3510 \times$. Additionally, compared with the sign-off STA tool, the GTN-Path achieves a speedup of $12 \times$.

Lookup table (LUT)-based libraries of standard cell characterization is crucial to accurate static timing analysis (STA). However, with the continuous scaling of technology nodes and the increasing complexity of circuit designs, the traditional nonlinear delay model (NLDM) is progressively unable to meet the required accuracy for cell modeling. The current source model (CSM) offers a more precise characterization of cells at advanced nodes and is able to handle arbitrary electrical waveforms. However, the CSM is highly time-consuming because it requires extensive transistor-level simulations, posing severe challenges to efficient standard cell library design. This work presents GTN-Cell, an efficient graph transformer network (GTN)-based method for library-compatible LUT-based CSM waveform prediction of standard cell characterization. GTN-Cell represents the transistor-level structures of standard cells as graphs, learning the local structural information of each cell. By incorporating the transformer encoder into the model and embedding path-related positional encodings, GTN -Cell captures the global relationships between distant nodes within each cell. Compared with HSPICE, the GTN-Cell achieves an average error of 2.27% on predicted voltage waveforms among different standard cells and timing arcs while reducing the number of simulations by 70%.