The conservation core accelerator presents a promising avenue for improving the computational efficiency of specific applications. However, its design space is ultra-high-dimensional, significantly increasing the exploratory effort required to identify the optimal design across performance, power, and area metrics. Furthermore, the discrete nature of the microarchitecture space renders conventional search methods ineffective. To tackle these challenges, we propose the Discrete Continuous Transformation to speedup Design Space Exploration, namely DCTDSE. It can operate in either offline or online mode. In offline mode, it transforms the original discrete design space into a continuous space, builds predictive models, performs parallel gradient-based optimization, and maps the results back to the discrete domain. In the online mode, DCTDSE refines the models by iteratively resampling previously found solutions, thereby enhancing exploration quality while maintaining moderate runtime overhead. Experimental results indicate that DCTDSE achieves a 3.9× to 40× speedup over benchmark methods in offline mode. In online mode, it provides a 2.5× speedup, with a 21% reduction in exploration quality relative to the most accurate comparison method.

With the advancement of technology nodes and the increasingly stringent requirements for stability, general yield analysis of customized circuits in the early stages of design has become a key bottleneck in manufacturing. In this article, we propose a multi-kernel sparse representation-based classification (MKSRC) method to enhance the efficiency and scalability of failure probability estimation by classifying tail samples. It employs class-balanced sampling to address data imbalance issues and utilizes multi-kernel features with adaptive kernel weights to enhance the accuracy and robustness of the classifier. Experimental results on 32-bit SRAM columns and analog circuits demonstrate that the proposed MKSRC method achieves higher classification accuracy and efficiency compared to other state-of-the-art methods, particularly in scenarios with limited training data. Compared to SOTA yield estimation methods, the MKSRC method achieves an average 2.57–3.29× improvement in both accuracy and efficiency, highlighting its ability to provide efficient and scalable yield analysis solutions for both SRAM and analog circuits.

Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture that warrants thorough design space exploration (DSE). However, traditional DSE methods for CGRAs often get trapped in local optima due to singularities, i.e., invalid design points caused by CGRA mapping failures. In this paper, we propose a singularity-aware framework based on the integration of reinforcement learning (RL) and imitation learning (IL) for DSE of CGRAs. Our approach learns from both valid and invalid points, substantially reducing the probability of sampling singularities and accelerating the escape from inefficient regions, ultimately achieving high-quality Pareto points. Experimental results demonstrate that our framework improves the hypervolume (HV) of the Pareto front by 23.56% compared to state-of-the-art methods, with a comparable time overhead.