Demo Data from EDBT 2026 / reviewers in the wild / expert
Qianhe Zhao
dblp:406/2601
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
0009-0006-1379-0576ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Compilers and program optimization · 75% Requirements engineering and software design · 25% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 100% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
deep learning compiler |
1.7 | 2 | 2025 | Sifter: An Efficient Operator Auto-Tuner With Speculative Design Space Exploration for Deep Learning Compiler · IEEE Trans. Computers 2025 Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate Hardware · IEEE Trans. Computers 2025 |
Requirements engineering and software design › design process
design space exploration |
0.9 | 1 | 2025 | Sifter: An Efficient Operator Auto-Tuner With Speculative Design Space Exploration for Deep Learning Compiler · IEEE Trans. Computers 2025 |
Compilers and program optimization › deep learning compiler
tensor program optimization |
0.9 | 1 | 2025 | Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate Hardware · IEEE Trans. Computers 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate Hardware · IEEE Trans. Computers 2025 |
Machine learning › Efficient and distributed learning › inference efficiency
inference optimization |
0.3 | 1 | 2025 | Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate Hardware · IEEE Trans. Computers 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator |
0.3 | 1 | 2025 | Sifter: An Efficient Operator Auto-Tuner With Speculative Design Space Exploration for Deep Learning Compiler · IEEE Trans. Computers 2025 |
Methods — techniques the papers use, named apart from their topics
intermediate representation · 2.6cost model · 2.6auto-tuning · 2.6speculative design space exploration · 1.7pruning rules · 1.7decision tree · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate HardwareabstractThe operator library is the fundamental infrastructure of deep learning acceleration hardware. Automatically generating the library and tuning its performance is promising because the manual development by well-trained and skillful programmers is costly in terms of both time and money. Tensor hardware has the best computing efficiency for deep learning applications, but the operator library programs are hard to tune because the tensor hardware primitives have many limitations. Otherwise, the performance is difficult to be fully explored. The recent advancement in LLM exacerbates this problem because the size of input data is not fixed. Therefore, mapping the computing tasks of operators to tensor hardware units is a significant challenge when the shape of the input tensor is unknown before the runtime. We propose DSAT, a deep learning operator performance autotuning technique for changeable-sized input data on tensor hardware. To match the input tensor's undetermined shape, we choose a group of abstract computing units as the basic building blocks of operators for changeable-sized input tensor shapes. We design a group of programming tuning rules to construct a large exploration space of the variant implementation of the operator programs. Based on these rules, we construct an intermediate representation of computing and memory access to describe the computing process and use it to map the abstract computing units to tensor primitives. To speed up the tuning process, we narrow down the optimization space by predicting the actual hardware resource requirement and providing an optimized cost model for performance prediction. DSAT achieves performance comparable to the vendor's manually tuned operator libraries. Compared to state-of-the-art deep learning compilers, it improves the performance of inference by 13% on average and decreases the tuning time by an order of magnitude. Pengyu Mu, Yi Liu 0013, Rui Wang 0014, Hangcheng An, Qianhe Zhao, Hailong Yang 0002, Chenhao Xie 0001, Zhongzhi Luan, Chunye Gong, Depei Qian 0001 |
IEEE Trans. Computers | 6 |
| 2025 | Sifter: An Efficient Operator Auto-Tuner With Speculative Design Space Exploration for Deep Learning CompilerabstractDeep learning compiler can automatically optimize operators. It provides higher flexibility compared to vendor libraries. However, existing DNN operator tuning methods mostly rely on search-based approaches, which still face challenges such as large design spaces and long tuning times. To address these issues, we propose Sifter, an efficient DNN operator auto-tuner with speculative design space exploration. By training and analyzing decision trees, we extract shared characteristics of high-quality schedules and summarize them as pruning rules. Applying these rules during the optimization allows us to speculatively explore the design space, minimize unnecessary hardware measurements, and shorten the optimization time without compromising the optimization result. We conducted experiments on three different platforms with various operators and models. The results demonstrate that Sifter reduces 52% of redundant schedules and shortens the optimization time by 41% while maintaining operator optimization performance at the state-of-the-art level. Qianhe Zhao, Rui Wang 0014, Yi Liu 0013, Hailong Yang 0002, Zhongzhi Luan, Depei Qian 0001 |
IEEE Trans. Computers | 1 |