Federico Buccellato

dblp:406/4450 · DBLP profile ↗
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4ranked-venue papers
3as first author
4since 2021 · last 2026
0009-0006-0562-4033ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 Hardware-Aware Runtime Detection of Soft-Error Anomalies in DPU-Accelerated Neural Networks
Federico Buccellato, Corrado De Sio, Sarah Azimi, Luca Sterpone
IOLTS1
2025 POSTER: AI-Powered Anomaly Detection for Satellite Telemetry
abstract
Reliable anomaly detection in satellite telemetry is critical for mission success, yet traditional threshold-based methods struggle with complex and evolving patterns.This work presents machine learning (ML) techniques to analyze high-dimensional telemetry data.Evaluations of real-world satellite telemetry datasets demonstrate the potential of ML to enhance spacecraft health monitoring and reduce manual intervention.
Federico Buccellato, Davide Nicolini, Eleonora Vacca, Corrado De Sio, Luca Sterpone
CF1
2025 POSTER: Hardware-Aware Software-Based Fault Injection Platform for DNN Accelerators
Eleonora Vacca, Federico Buccellato
CF2
2025 On-Hardware Resilience Analysis of DPUAccelerated CNNs on FPGA-Based Systems
abstract
In recent years, Reconfigurable SoCs have emerged as a high-performance solution for embedded systems, addressing the increasing complexity of neural networks, balancing performance, cost, and adaptability. Flexible hardware accelerators, such as AMD’s Deep Learning Processing Units (DPUs), enable efficient computation across various domains, including safety-critical applications. However, soft errors remain a significant reliability concern, especially in harsh environments like space, where radiationinduced corruption of configuration memory poses a significant threat to FPGA-based systems. Most research on the reliability and robustness of deep learning models against soft errors has focused on application-level analyses, with comparatively little attention paid to architectural hardware faults. This paper introduces a resilience evaluation framework targeting AMD’s state-of-the-art DPU, comparing traditional application-level fault injection with hardware-aware fault injection performed on an actual hardware platform, a Kria KV260. Applying this methodology, we evaluated fourteen different deep neural network architectures and demonstrated that hardware-aware fault injections reveal critical vulnerabilities that applicationonly approaches fail to detect. Moreover, we investigated the source of different faults at the hardware level, enabling the identification of architectural resources that are more susceptible to errors. These insights are valuable to support the development of more robust deployment strategies and mitigation techniques tailored to FPGA-based deep learning accelerators.
Federico Buccellato, Corrado De Sio, Sarah Azimi, Luca Sterpone
DSD1