Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Jason Zellmer

dblp:407/9524 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0000-5365-9050ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Hardware security and side channels · 77% Systems and software security · 23%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution defense
0.912025
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.912025
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025
Processor architecture and microarchitecture
speculative execution
0.912025
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025
Systems and software security
memory safety
0.312025
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025
Systems and software security › memory safety › hardware-enforced memory safety
memory tagging
0.312025
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization · ISCA 2025

Methods — techniques the papers use, named apart from their topics

speculative address sanitization · 1.7control-flow integrity · 1.7ARM Memory Tagging Extension · 1.7
YearPublicationVenuePosition
2025 SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization
abstract
Transient execution attacks (TEAs), such as Spectre and Meltdown, exploit speculative execution to leak sensitive data through residual microarchitectural state.Traditional defenses often incur high performance and hardware costs by delaying speculative execution or requiring additional shadow structures and dynamic information flow tracking.In contrast, our approach models these attacks as violations of software-defined security contracts and enforces these contracts in hardware using existing features.We introduce Speculative Address Sanitization (SpecASan), which leverages ARM's Memory Tagging Extension (MTE) to extend memory safety protection from the committed path to the speculative path.When a speculative access does not pass the MTE tag comparison, this access is delayed until speculation resolves.This ensures that only validated accesses affect the microarchitectural state while preserving the performance benefits of speculation.When combined with Control-Flow Integrity (CFI) enforcement mechanisms, already supported by some hardware implementations, our evaluation shows that SpecASan effectively mitigates a broad class of transient execution attacks, including Spectre and Microarchitectural Data Sampling (MDS).Furthermore, SpecASan achieves this with low performance overhead and minimal hardware complexity, highlighting its practicality and efficiency.
Saber Ganjisaffar, Esmaeil Mohammadian Koruyeh, Jason Zellmer, Hodjat Asghari Esfeden, Chengyu Song, Nael B. Abu-Ghazaleh
ISCA3