Mingzhuo Yin

dblp:408/0818 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0009-1495-5426ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 89% High-performance computing · 5% Parallel and multicore computing · 5%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.912025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
Memory systems › cache
cache miss reduction
0.912025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
Memory systems › cache › prefetching
indirect memory access prefetching
0.912025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
Memory systems › cache
prefetching
0.912025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
Memory systems
software prefetching
0.912025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
Parallel and multicore computing
graph processing
0.312025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025
High-performance computing
sparse linear algebra
0.312025
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access · ISCA 2025

Methods — techniques the papers use, named apart from their topics

loop analysis · 0.9dependence graph extraction · 0.9compiler analysis · 0.9
YearPublicationVenuePosition
2025 Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access
abstract
Graph analytics and sparse linear algebra applications heavily rely on indirect memory access (IMA).IMAs are characterized by poor temporal and spatial locality, which causes frequent high-latency DRAM accesses.While dedicated hardware prefetchers for IMA have been explored, they target narrow access patterns and tend to introduce significant hardware complexity.Software prefetching offers a promising alternative, leveraging compiler analysis to prefetch indirection patterns.However, existing software prefetchers struggle with sparse applications due to limited loop iterations and complex IMA patterns across nested loops.We propose Magellan, a novel loop-guided software prefetcher designed to detect and schedule IMA prefetches efficiently.Magellan introduces two key innovations: (1) extracting dependence graphs across loop levels to detect complex IMA patterns and (2) capturing inner-outer loop semantics to prefetch for both current and future iterations.We evaluate Magellan on 14 memory-intensive benchmarks using real-world datasets from social networks and web graphs.Compared to the best existing IMA software prefetcher, Magellan reduces cache misses by 25% and dynamic instruction counts by 14% on average.This results in a 1.14× average speedup, with performance gains of up to 1.41×.
Gelin Fu, Tian Xia 0008, Mingzhuo Yin, Prashant J. Nair, Mieszko Lis, Pengju Ren
ISCA3