Clock duty-cycle distortion caused by aging effects, which induces circuit performance degradation, has become a significant concern in advanced processes. We propose a digital two-stage duty-cycle corrector (DCC) that directly corrects the duty-cycle distortion, using a duty-cycle adjuster (DCA) for coarse duty-cycle width modulation followed by a high-accuracy half-cycle delay line (HCDL) for 50% duty-cycle correction. The two-stage structure further extends the operating frequency and duty-cycle range, while achieving low correction latency through the elimination of external complex control by employing open-loop logic as compared with state-of-the-art (SOTA) works. Implemented in a 22nm ULVT CMOS process, measurement results show that it operates at a frequency range of 250M to 2.5GHz with an acceptable input duty-cycle range of 10% to 90%. It achieves a maximum duty-cycle correction error of 1.5% at 2.5GHz and correction latency of only three clock cycles. The maximum peak-to-peak jitter of the output clock is 13.25ps.

The on-chip droop in processor may cause a severe voltage reduction resulting in a need for on-chip voltage droop detectors. Basically, the digital droop detector indirectly senses voltage changes by reading out the delay information affected by the voltage through a time-to-digital converter (TDC). Conventional all-digital droop detector based on the ring oscillator TDC suffers from high power and area overhead. In order to reduce power consumption and area overhead without introducing the problem of metastability, two techniques are proposed. One is the multi-phase clock sampling technique to achieve the ring stage number compression, therefor the number of sampling register is diminished. The other one is the coarse-fine sharing Nyquist counter for anti-metastability, thus reducing the number of counter. Even with the introduction of the additional all-digital multi-phase clock generator, this design can still achieve an advantage in power and area consumption. Designed at 22nm process, hspice simulations show that the power consumption is reduced by 16.4% and the area is reduced by 12.4% as compared to the SOTA.

Timing error detection and correction (EDAC) in resilient circuits helps eliminate excess timing margins. However, it faces misdetection risks when critical paths (CPs) remain inactive. We propose a 15-transistor timing error and path-activation detector (TEPD) capable of detecting both timing violations in late-arriving signals and CP activation, with robust operation down to 0.33 V. Regarding circuit-level error correction, we introduce an error-correcting flip-flop (ECFF), leveraging time-borrowing for zero-cycle response latency without requiring pipeline refresh. The custom-optimized ECFF adds only six transistors, increasing delay, dynamic power, and static power by 15%, 11%, and 14%, respectively, compared with a standard flip-flop, ensuring efficient error correction with minimal cost. A system-level voltage tuning strategy is further developed to handle continuous timing errors, ensuring robust adaptive voltage scaling (AVS) operation. Implemented on a neural network (NN) accelerator in the 28-nm CMOS, the system operates across a wide voltage range from 0.54 to 0.9 V. It achieves up to 52% power gain or 123% frequency gain at the near-threshold region, with negligible area and power overhead compared with the margined baseline.