In this work, we present an energy- and area-efficient soft reset integrate-and-fire (SRIF) neuron circuit for spiking neural networks (SNNs), designed to improve inference accuracy by retaining the residual membrane potential above the firing threshold. The conventional current-subtraction soft reset neuron introduces significant performance overhead. In contrast, the proposed SRIF neuron employs the charge-sharing mechanism, characterized by its simple structure and minimal energy overhead. The 28-nm CMOS SRIF neuron exhibits an energy consumption of 14.7 fJ per spike and occupies an area of 107 µm2. Additionally, the soft reset mechanism achieves a 39.5% improvement in inference accuracy compared to the hard reset baseline when benchmarked with VGG-11 network trained on the CIFAR-10 dataset. Moreover, a capacitor-sharing strategy is proposed to improve the utilization efficiency of reset capacitors, providing 1.24x smaller neuron area.

In this work, we propose a refresh-reduction 3T1C eDRAM-based digital Compute-In-Memory (CIM) macro with an asymmetric error tolerance scheme to improve the energy consumption caused by frequent refresh operations. The novel asymmetric error tolerance scheme is first implemented in an eDRAM-based CIM macro to mitigate the effects of the wrong weights, extending the refresh period of the eDRAM cell. 3T1C eDRAM cell exhibits precise asymmetric error behavior, perfectly adapting the proposed asymmetric error tolerance scheme. Additionally, a reconfigurable refresh controller is introduced to eliminate refresh performance overhead during CIM operations and further reduce power consumption by reusing CIM readout data. The proposed 128Kb eDRAM-based CIM macro, simulated at 28nm, achieves a 98-100% improvement in the refresh period and a 21.5% improvement in average energy efficiency at 25°C and 60°C.

In the conventional RRAM design, differential reading for odd and even bitlines (BLs) facilitates high-speed data retrieval, but this comes at the cost of area overhead due to additional multiplexers, and is prone to causing performance degradation with inaccurate timing signals. In this work, a high performance RRAM macro is presented to solve the above problems through: 1) a compact dual-wordline (WL) array structure that splits the WLs into odd and even pairs, the inactive half of the BLs can be used as differential input without the extra multiplexers, thereby improving the storage density and reducing WL switching power consumption by 45%; 2) a replica BL control circuit to effectively track the BL discharge characteristics and accurately control WL pulse width, thus lowering read energy consumption and latency. A 1Mb RRAM macro with 64-bit bandwidth and 8.85Mb/mm2storage density is implemented using 28nm process, achieving a 3.5ns read cycle and consuming 9fJ per bit during reads, with the FoM (read throughput / area) at least 3.6× higher than prior works.