Zhuojian Yao

dblp:409/9843 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021
YearPublicationVenuePosition
2026 A 1-10.7GHz Low-Jitter 8-Phase Injection-Locked Clock Generator with Supply-Voltage Feedback in 28 nm CMOS
Haikun Jia, Wei Deng 0001, Zhuojian Yao, Angxiao Yan, Baoyong Chi
ISCAS5
2026 A 30MHz-BW Continuous-time Delta Sigma Modulator with Reference Rotation and Time Constant Calibration in 65nm CMOS
Zhuojian Yao, Haikun Jia, Lilan Yu, Wei Deng 0001, Baoyong Chi
ISCAS1
2026 Iterative Time-Constant Tuning for Finite-GBW Compensation in Continuous-Time Delta-Sigma Modulators
Jianhao Yuan, Zhuojian Yao, Baoyong Chi
ISCAS2
2025 A Total Noise Power Based Digital Calibration Method for Continuous-Time Delta-Sigma Modulators
abstract
This paper analyzes the relationship between the total output noise power and loop filter coefficients variation of continuous-time delta-sigma modulators. Based on the analysis, a new calibration technique utilizing the total output noise power to improve the loop filter inaccuracy caused by PVT variation is proposed. This proposed calibration method is implemented in the digital domain and requires only capacitor arrays in analog loop, minimizing the hardware cost and the excess loop delay. The calibration technique is verified by a third-order delta-sigma modulator post-layout simulation results. The peak signal-to-noise-and-distortion ratio (SNDR) increased by 4.5dB after calibration.
Zhuojian Yao, Haikun Jia, Lilan Yu, Wei Deng 0001, Baoyong Chi
ISCAS1