To effectively transmit data to and from satellites requires a complex and robust RF communication system. Using adaptive link techniques, several different types of signal modulations may be used to maximize satellite efficiency depending on a variety of unexpected channel impairments. We propose an FPGA based neural network system capable of learning these RF signal modulations using a supervised learning technique designed for low power, high-efficiency in-orbit deployment. Thus, as signal modulation changes, a receiving satellite would be able to recognize this modulation update without adjustment from an operator, or any delay due to control signal transmission.Due to the limited resources of FPGAs, we implement CNN transfer learning on the FPGA instead of full CNN training. The work presented demonstrates a convolutional neural network (CNN) capable of learning and recognizing a set of modulation schemes commonly used to transmit RF information. We are capable of recognizing the modulation scheme from the I and Q data channels directly, with no preprocessing or data conversion required other than segmenting the incoming signal into a set of uniform normalized samples. We perform a network design and size analysis, showing that we can obtain reasonably high accuracy using networks with a relatively low number of trainable parameters. Thus, modulation recognition can be performed through rapid feedforward computation. Given that a user of this system may wish to receive a signal using a modulation scheme that the network has not previously learned, we demonstrate that transfer learning can learn new modulation schemes by retraining only the fully connected layers in the CNN. Thus, this type of network would excel in outer space deployment using high-efficiency transfer learning hardware. Our FPGA system utilized 2.1W power and processed 219 data samples per second for training. This made it about 59x more energy efficient than a desktop GPU for the same task.

The ever-increasing use of Internet of Things (IoT) devices results in the implementation of multiple wireless technologies that would not only cater their data rate requirements but also support various applications. To optimize the energy efficiency and security of the wireless transmission, it is imperative to identify the wireless technologies in various IoT implementations. Many of the existing approaches are based on measuring only the receiving signal strength indicator (RSSI). However, such approaches may not work well because of transmit power control and complex channel variations among different wireless technologies. In this article, we propose an autonomous wireless detection scheme that considers multiple distinguishable physical (PHY)-layer settings for real-time identification of wireless technologies for real-time applications. Specifically, the proposed scheme relies on the PHY-layer measurements of the targeted spectrum. Transmission settings, such as bandwidth, carrier frequency, and RSSI are estimated from the raw in-phase and quadrature-phase (I/Q) measurements. In addition, a symbol-level extraction scheme is implemented to extract unique features of modulation settings. These aforementioned features are applied to a machine learning process to identify the received wireless technologies. Compared with raw I/Q measurements, the extracted features are much simplified and, thus, the machine learning classifier can be designed with a simple structure for fast processing on IoT nodes. The proposed schemes are primarily evaluated theoretically, followed by implementing them on a USRP software-defined radio (SDR)-based hardware testbed. The evaluation results demonstrate high accuracy in the real-time detection of different wireless technologies for seamless IoT applications.

The rapid growth of Internet-of-things (IoT) devices modernizes our society and lives. Such a growth leads to the pro-liferation of the wireless technologies, most of which occupy the unlicensed/open industrial, scientific and medical (ISM) bands. Since each of these wireless technologies adheres to different standards, they give rise to challenges like cross technology interference, incompatible security protocols and high energy consumption. In this work, we envision to achieve an energy-efficient communication on a seamless IoT platform. In specific, a game theoretical approach is proposed to formulate a multi-device IoT communication system. The existence and uniqueness of the Nash equilibrium is proven to achieve the optimal transmit power for the IoT devices. Moreover, a distributed scheme is developed for practical implementations depending on receiving signal strength indicators. Simulation results demonstrate that optimal transmit power can be achieved through the proposed scheme. We further implement and demonstrate the distributed approach on a universal software radio peripheral (USRP) testbed.

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared to traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see which memristor device structures are most suitable for applications in reconfigurable computing. In this paper, we demonstrate the programmability of memristor devices with filamentary switching based on LiNbOx, a new resistive switching oxide. We have performed several characterization experiments that demonstrate the high resolution programmability of these devices. Once the optimal programming voltages and conductivity ranges for these memristor devices are determined, a method is presented to determine how many unique states can be achieved in these devices. Parameters obtained from this analysis can greatly strengthen memristor device models that implement realistic stochastic switching behavior. We show that 11 unique states can be stored in this device with 95% confidence, but many more states are achievable using feedback write techniques or in-situ learning. Therefore, we have determined that Lithium Niobate memristors are strong candidates for use in neuromorphic computing.

This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

The recently discovered memristor has the potential to be the building block of a high-density memory system. A memristor based crossbar memory system was analyzed in terms of timing and switching energy using SPICE. The memristor model in the simulations was designed to match the I-V characteristics of three different published devices. The simulation results for each device were compared to demonstrate the performance of a one transistor one memristor (1T1M) memristor crossbar.

A memristor based write circuit is presented that can update multiple memristors using a neuron spike generated by the Izhikevich model. A memristor read circuit is also presented that is capable of quantizing the resistance into 5 discrete values that could be digitally decoded. Together, these circuits provide the basic block for a memristor based neuromorphic architecture. The memristors were modeled using published device characterization data.

As semiconductor devices have shrunk further into the nanoscale regime, a new device, the memristor, has been discovered that has the potential to transform neuromorphic computing systems. This device is considered as the fourth fundamental circuit element. It was first theorized by Dr. Leon Chua in 1971 and has been discovered by HP labs in 2008. This paper describes initial efforts at fabricating the memristor devices and examining their properties. Two versions of memristor devices have been fabricated at the University of Dayton and the Air Force Research Laboratory utilizing varying thicknesses of the TiO2dielectric layers. Our results show that the devices do exhibit the characteristic hysteresis loop in their I-V plots. Further refinement in the devices to achieve stronger hysteresis will be carried out as future work.