Large language models (LLMs) used for multiple-choice and pairwise evaluation tasks often exhibit selection bias due to non-semantic factors like option positions and label symbols.Existing inference-time debiasing is costly and may harm reasoning, while pointwise training ignores that the same question should yield consistent answers across permutations.To address this issue, we propose Permutation-Aware Group Relative Policy Optimization (PA-GRPO), which mitigates selection bias by enforcing permutation-consistent semantic reasoning.PA-GRPO constructs a permutation group for each instance by generating multiple candidate permutations, and optimizes the model using two complementary mechanisms: (1) cross-permutation advantage, which computes advantages relative to the mean reward over all permutations of the same instance, and (2) consistency-aware reward, which encourages the model to produce consistent decisions across different permutations.Experimental results demonstrate that PA-GRPO outperforms strong baselines across seven benchmarks, substantially reducing selection bias while maintaining high overall performance.The code is available on GitHub.

RELION is a widely-used software suite for cryoelectron microscopy (cryo-EM) single-particle analysis (SPA), yet its performance optimization has primarily focused on x86 CPUs and NVIDIA GPUs. In this work, we present the first systematic effort to optimize RELION on modern many-core CPUs. Through detailed performance analysis, we identify critical bottlenecks across RELION's major computational stages. We then apply a set of software- and hardware-aware optimizations, including vectorization optimization, process and thread configurations tuning, algorithm optimization, lock optimization, memory affinity optimization, and computation redundancy optimization. Our optimized version achieves significant speedups and exhibits better scalability than the original RELION across all stages. Notably, it outperforms a single NVIDIA A100 GPU on the complete SPA workflow, achieving a$2.22 \times$speedup on the SPA dataset and a$1.13 \times$speedup on the RELION Benchmark dataset. Validation experiments further confirm that our optimizations preserve the reconstruction accuracy, demonstrating the potential of specific CPU architectures as a competitive and efficient platform for cryo-EM data processing.

Workload execution can account for 90% of the total database knob tuning time, which is often the bottleneck for efficient knob tuning in practice. Reducing the tuning time by using a compressed workload is a natural solution. However, many existing workload compression methods are designed for OLAP workloads, which reduce the number of queries needed for analysis tasks by sampling a small subset of queries. These methods are less effective for OLTP workloads in knob-tuning tasks, as they often disregard essential contextual details, including query sequence and concurrency. As a result, configurations that perform well on the compressed OLTP workload may not deliver similar competitive performance on the original workload. To address these challenges, we first define the objective of OLTP workload compression for knob tuning. We then propose a slice-based compression method, SCompression , which compresses workloads by slicing based on time intervals while preserving concurrency. SCompression achieves the objective by focusing on generating a compressed workload that (1) executes faster than the original workload and (2) produces performance variations similar to the source workload under different configurations. SCompression works in three steps: (1) dividing the workload into segments to capture regular performance fluctuations, (2) slicing each segment to preserve concurrency and transaction context, and (3) sampling slices under execution time constraints using a cluster-based approach to ensure representativeness. Finally, SCompression replays the compressed workload to produce the performance that mirrors the source workload. Extensive experiments on real-world and benchmark OLTP workloads show that SCompression is a cost-effective solution for knob tuning, accelerating tuning by up to 40× with only a 5% performance reduction.

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms(1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only$90~\mu \text{W}$associated with the FLL.

Superpoints are formed by grouping similar points with local geometric structures, which can effectively reduce the number of primitives of point clouds for subsequent point cloud processing. Existing superpoint methods mainly focus on employing clustering or graph partition to generate superpoints with handcrafted or learned features. Nonetheless, these methods cannot learn superpoints of point clouds with an end-to-end network. In this paper, we develop a new deep iterative clustering network to directly generate superpoints from irregular 3D point clouds in an end-to-end manner. Specifically, in our clustering network, we first jointly learn a soft point-superpoint association map from the coordinate and feature spaces of point clouds, where each point is assigned to the superpoint with a learned weight. Furthermore, we then iteratively update the association map and superpoint centers so that we can more accurately group the points into the corresponding superpoints with locally similar geometric structures. Finally, by predicting the pseudo labels of the superpoint centers, we formulate a label consistency loss on the points and superpoint centers to train the network. Extensive experiments on various datasets indicate that our method not only achieves the state-of-the-art on superpoint generation but also improves the performance of point cloud semantic segmentation. Code is available at https://github.com/fpthink/SPNet.

In this paper, a low voltage high accuracy 10- transistor power-on-reset circuit with brown-out-reset function is proposed. A native NMOS current reference based architecture is proposed to get high accuracy trip-voltage with a small area and power consumption. By adjusting the number of native NMOS transistors, a stable hysteresis window is obtained. Post-layout simulation results based on SMIC 55nm CMOS process show that the trip-voltage deviation of the proposed power-on-reset circuit is only 34mV under different temperature and process corners. Also, the trip-voltage of the proposed power-on-reset circuit shows great robustness to supply ramp time. The power consumption of the proposed circuit is as low as 36nW at 0.5V. Since the proposed power-on-reset circuit consists of only 10 transistors, the area is as low as 67.5μm2.

As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true-single-phase-clocked (TSPC) FF is proposed. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Postlayout simulations based on SMIC 55-nm CMOS technology show that at a supply voltage of 1.2 V, the power consumption of the proposed FF is 84.37% lower than that of conventional transmission-gate flip-flop (TGFF) at 10% data activity. The reduction rate is increased to 98.53% as the data activity goes down to 0%. When the supply voltage decreases to 0.6 V, the proposed FF consumes only 0.411 fJ/cycle at 10% data activity, which is 84.23% lower than TGFF. Measurement results of ten test chips demonstrate the great energy efficiency of the proposed FF. Furthermore, the CK-to-Q delay of the proposed FF is 26.18% lower than that of TGFF at a supply voltage of 1.2 V.