This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

Convolutional Neural Networks (CNN) are widely adopted for Machine Learning (ML) tasks, such as classification and computer vision. GPUs became the reference platforms for both training and inference phases of CNNs due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. However, the literature presents gaps regarding analyses and comparisons of these accelerators to evaluate Power-Performance-Area (PPA) trade-offs. Typically, the literature estimates PPA from the number of executed operations during the inference phase, such as the number of MACs, which may not be a good proxy for PPA. Thus, it is necessary to deliver accurate hardware estimations, enabling design space exploration (DSE) to deploy CNNs according to the design constraints. This work proposes a fast and accurate DSE approach for CNNs using an analytical model fitted from the physical synthesis of hardware accelerators. The model is integrated with CNN frameworks, like TensorFlow, to generate accurate results. The analytic model estimates area, performance, power, energy, and memory accesses. The observed average error comparing the analytical model to the data obtained from the physical synthesis is smaller than 7%.

GPUs became the reference platform for both training and inference phases of Convolutional Neural Networks (CNN) due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. The design space exploration of CNNs using standard approaches, such as RTL, is limited due to their complexity. Thus, designers need frameworks enabling design space exploration that delivers accurate hardware estimation metrics to deploy CNNs. This work proposes a framework to explore CNNs design space, providing power, performance, and area (PPA) estimations. The heart of the framework is a system simulator. The system simulator front-end is TensorFlow, and the back-end is performance estimations obtained from the physical synthesis of hardware accelerators, not only from components like multipliers and adders. The first set of results evaluate the CNN accuracy using integer quantization, the accelerators PPA after physical synthesis, and the benefits of using a system simulator. These results allow a rich design space exploration, enabling selecting the best set of CNN parameters to meet the design constraints.

Multi-processor Systems-on-Chip (MPSoCs) have been proposed to tackle embedded systems' requirements due to their potential for low-power consumption and high scalability. These systems fit the needs of many application domains, including robotics and autonomous vehicles, in which reliability, performance, and timeliness are critical to operation. In this paper, we propose an integrated environment for the development of robotic applications targeting MPSoCs. The proposed environment eases the evaluation of non-functional requirements by combining cycle-accurate simulations from RTL models with behavioral simulations from robotics. We present a case study of the proposed environment in the context of a UAV (unmanned aerial vehicle) stabilization software, providing performance and energy estimations for different software implementations.

This work presents GoDonnie a programming language to command a robot to improve orientation and mobility(O&M) skills in people who are visually impaired (PVI). The GoDonnie programming language is based on the Logo language. GoDonnie runs in a programming environment called Donnie. This environment has a 2D graphic simulator with a virtual robot, in which one can visualise and receive sound feedback from the execution of the language commands for moving the virtual robot in the environment. GoDonnie has been evaluated with PVI to verify its usability and support to O&M. The results indicate that GoDonnie has good usability, supports the development of O&M in PVI and meets the expectations regarding the programming environment. A video of GoDonnie execution is available in https://youtu.be/HE__sAgfNBo

Energy efficiency has become one of the most common and important demands for contemporary applications, increasing the desire for chips that operate near the threshold voltage levels, which unfortunately worsens the effects of process, voltage, and temperature (PVT) variability. An alternative solution to cope with PVT variations are the timing resilient architectures, such as the synchronous Razor family and the asynchronous Blade template, that rely on error detection logic (EDL) to detect and recover from timing violations. On one hand, the use of timing resilient architectures makes the path delay testing more challenging because it is not a matter of simple pass or fails the test. On the other hand, we show that timing resilient architectures, such as Blade, present opportunities to design low-cost online delay testing of the critical paths. Results show the area overhead and fault coverage using functional testing on a 32-bit MIPS CPU and a crypto core.

Most recent timing resilient templates are using asynchronous design techniques and integrating both flip-flops and latches in their design to enable more aggressive performance improvement and reduction in energy consumption. Despite these benefits, they impose challenges in terms of testability because both latches and flip-flops typically use different test protocols. This paper presents an optimized scan cell for flip-flops which is compatible with the protocol used by scannable latches. By using the proposed cell, it is possible to have latches and flip-flops in the same scan chain and the DfT flow fully automated by commercial EDA tools. Experimental results show that the proposed cell reduces silicon area, leakage, and dynamic power compared to the original cell.

The Software-Defined Networking (SDN) is a communication paradigm adopted in computer networking. The SDN assumes simple and programmable routers, removing the control logic from the routers' level, and assigning it to a high-level controller (software), which is responsible for defining the path of the communication flows at run-time. The controller can implement different communication rules to define the paths, as Quality-of-Service (QoS), fault-tolerance, and security. Many-cores may adopt the SDN paradigm due to its advantages: reduced hardware complexity, high reusability, and flexible management of communication policies. However, the challenge to apply the SDN may be the overhead for defining the paths in software against hardware-based approaches. The goal of this paper is to show that SDN can be a viable alternative for NoC management in many-core systems. This work proposes a generic SDN architecture for many-cores, detailing both the hardware and software designs. We compare the quality of the proposal with a state-of-the-art search path mechanism (hardware implemented), in a QoS case-study providing Circuit-Switching (CS) for applications. Results show that the SDN paradigm achieves similar performance than the hardware-based technique regarding path length. Hardware implemented mechanisms present a reduced latency to establish the paths. As the path establishment occurs once for each application flow, results show that the search path latency of SDN is not an actual drawback, as it could be expected.

Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.

Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard global timing boundary. The use of latches emerges as a possible solution to the contemporary design challenges such as clock skew/jitter, PVT variation, and low-power and high-performance designs. Moreover, latches are also gaining popularity among asynchronous and timing resilient circuits. One of the available scannable cells for latches is called level sensitivity scan-based design (LSSD). The goal of this brief is to present an open design of an optimized single-latch LSSD cell, which has better tradeoffs between propagation delay, power, energy, and silicon area than the original LSSD design, thus reducing the cost for testing latch-based designs.

Fault handling mechanisms become more relevant as systems integrate more hardware logic. For instance, current multi-processor system-on-chips (MPSoCs) consists of hundreds of processors connected by an interconnection network. This type of system can only be cost effective if it can handle faults on its main components (i.e. processors and interconnect). Traditional fault recovery approaches for multi-processors were adapted from the domain of cluster of computers and might be more complex than required for common MPSoC applications domains. This paper presents a lightweight online fault recovery for embedded processors of MPSoCs based on distributed memory. This approach automatically restarts affected applications reallocating tasks to healthy processors. All steps are performed at the kernel level, without changing user application code. Results show very short recovery time, from 110 μs to 425 μs with a 100MHz clock, which are mostly dominated by the size of the reallocated tasks.

The continuing development of the silicon technology leads to systems with hundreds of processors interconnected by a network on chip (NoC-based MPSoCs). On one hand, the nanotechnology enables to develop such complex systems, but, on the other hand, the vulnerability to faults increases. The literature presents partial fault-tolerant approaches, targeting specific parts of the system, as high-level methods, router level, link level, and routing algorithms. There is an important gap in the literature, with an integrated method, from the fault detection at the router level up to the fault recovery and correct execution of applications in a real MPSoC. This is the goal of the present work, to present a method with fault-tolerant techniques from the physical to the transport layers. The MPSoC is modeled at the RTL level, using VHDL. A fault campaign injection (5 simultaneous injected faults) resulted in 2,000 simulated scenarios. Results demonstrated the effectiveness of the proposal, with most of the scenarios working correctly with routers operating in degraded mode, with an impact on the execution time below 1%.

Analysis by Transcriptogram was developed as a solution to reduce the noise in the micro array measuring technique of the Transcriptome, and has demonstrated potential to be applied as a method of disease diagnostics. The noise reduction in the measurement is achieved by ordering the proteins of a given protein interaction network in a linear way, allowing gene expression analysis in whole genome scale. The ordering process uses a seriation technique, which models a protein-protein association network into an undirected graph. So far, the viability of the diagnosis method was hindered by the high runtime of the ordering algorithm, since the Homo sapiens network can have around 30 thousand proteins. This paper presents some optimizations applied to the seriation problem, which lead to a significant reduction of execution time and the problem complexity analysed. Results show that the algorithm produces good results in reasonable time, e.g. Order an undirected network of 9684 nodes in about 35 minutes, which is faster if compared with other seriation techniques evaluated.

Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.

The advances in deep submicron technology have made the development of large Multiprocessor Systems-on-Chip (MPSoC) possible and Networks-on-Chip (NoCs) have been recognized to provide an efficient communication architecture for such systems. With the positive effects on the device's integration some drawbacks arise, such as the increase of fault susceptibility during the MPSoC manufacturing and operation. This work presents Phoenix, which is a direct mesh NoC that implements fault tolerant mechanisms in order to enable end-to-end communication when some links fail. Phoenix implements a distributed fault tolerant mechanism in software (i.e. in each processor) and in hardware (i.e. in each router). Experimental results show that Phoenix is scalable and allows the MPSoC operation even in the presence of several faulty links.

Advances in design integration have enabled the integration of large Multiprocessor Systems-on-Chip (MPSoC). Such systems are prone to the execution of complex applications if high degree of parallelism is employed on the communication infrastructure. Network-on-Chip (NoC) has emerged as a new communication paradigm for large MPSoCs with advantages such as the increase of reliability on components interactions. However, device's integration may convey few shortcomings during MPSoC manufacturing and operation, for instance, the vulnerability to faults. This paper describes Phoenix, which is a direct mesh NoC with fault detection scheme. The proposed architecture explores a fault-tolerant mechanism, which is implemented in a distributed manner as a fault monitor on processors and routers. Results demonstrate that Phoenix can be scalable in view of the stabilization time regarding to faults incidence, allowing MPSoC operation even with the occurrence of a large number of faults.

The yield of homogeneous network-on-chip based multi-processor chips can be improved with the addition of spare tiles. However, the impact of this reliability approach on the chip energy consumption is not documented. For instance, in a homogeneous MPSoC, application tasks can be placed onto any tile of a defect-free chip. On the other hand, a chip with defective tile needs a special task placement, where the faulty tile is avoided. This paper presents a task placement tool and the evaluation of energy consumption of homogeneous NoC-based MPSoCs with spare tiles. Results show NoC energy consumption overhead ranging from 1 to 10% when considering up to three faults randomly distributed over the tiles of a 3×4 mesh network. The results also indicate that faults on the central tiles typically have more impact on energy overhead.

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.

This paper presents new DfT modules required to use networks-on-chip as test access mechanism. The paper demonstrates that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. The DfT modules was analysed in terms of silicon area and test time, considering different network and test configurations.

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Æthereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM.

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increase in the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC'02 benchmarks and on two open core processors, compliant with MIPS and SPARC instruction sets. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins.

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a simple microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.