Seismic processing is an important technology in petroleum industry. During the execution of seismic processing applications, large amount of intermediate data are generated and accessed. Providing high-performance services for intermediate data in the traditional storage architecture is expensive. In addition, because of the existence of new storage devices, the heterogeneity of storage environment has brought much inconvenience to the application developers and petroleum scientists. In this paper, we present a hierarchical intermediate data storage system called HIDStore. HIDStore employs distributed storage system based on the local storage devices and idle network resources to accelerate intermediate data access. Our experiments show that using HIDStore could improve the performance of various seismic processing applications and the resource utilization in compute cluster. HIDStore also abstracts different kinds of storage devices into hierarchical logical volumes and provides easy-to-use API to access data. Developers could deal with intermediate data in a high level of abstraction. Applications based on the HIDStore could fit into different storage environment and gain optimal performance automatically. Intermediate data in HIDStore could be automatically evicted once they expire.

The authors present a novel DFT technique based on multimode Illinois scan architecture (MILS) for low pin count test that simultaneously reduces test data volume and test application time. By using the proposed technique, significant savings in test data volume, and testing time can be obtained without modifying the clock tree of the design and with a very small combinational area overhead. Experimental results for two large industrial circuits show that the test data volume and test application time reduction of the order of 100times can be achieved in all cases with less than 1% area overhead over ILS.

This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach

For nanometer designs, many subtle defects lead to excessive delays in signal paths that cause reliability concerns. Traditional test-based diagnosis methods can only identify the failing nodes without the capability to tell the defect nature behind the observed delay faults. This differentiation is important for gathering accurate defect statistics for process improvement during yield ramp-up. In this paper we presented an effective delay defect analysis methodology that can quickly categorize the delay defects into either transistor related defects or resistive interconnect defects. The new delay defect/failure characterization method is based on low voltage test and delay defect detection in slack interval (DDSI) method. Experimental results were presented to validate the effectiveness of the new method. Practical considerations were also addressed for adoption of the methodology.

A new delay-testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. The simulation showed orders of magnitude delay defect detection efficiency improvement. In this paper we investigated the yield loss problem and proposed a practical production test based on delay defect detection in slack interval (DDSI).

A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. We evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The simulations are performed using a simple switched RC (resistor-capacitor) switching delay model. The results indicate that the new delay testing approach is orders of magnitude more effective in detecting and diagnosing smaller delay defects that increase circuit path delays by 10-50%. The new methodology can address increasing concerns that failure to detect such small delay faults during test may be the cause of significant unreliability in emerging nanometer technologies.