We present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for any length of message in parallel. For a given message with any length, we first divide the message into blocks, each of which has a fixed size equal to the degree of the generator polynomial. Then we perform CRC computation among the blocks in parallel using Galois field multiplication and accumulation (GFMAC). Theoretically, our fast parallel CRC algorithm can achieve unlimited speedup over the bit-serial algorithm or byte-wise table lookup algorithm at the expense of adding enough GFMAC units. Our algorithm can perform CRC computation for any lengthy message with two to three clock cycles. In practice, we choose to use a configurable processor where a customized instruction is added to perform multiple pairs of GF multiplication and accumulation. For example, a 4-GFMAC implementation can compute a 32-bit CRC in two to three cycles for a 16-byte message. This level of performance is hundreds of times faster than a bit-serial CRC algorithm or tens of times faster than a byte-wise parallel CRC algorithm. The generator polynomial can be chosen to be software programmed or hard-coded. Our algorithm adds only a small number of logical gates to the processor core.

New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processor function units and the associated software environment - compilers, debuggers, simulators and real-time operating systems - satisfies these needs. At the same time, designing at the level of software and instruction set architecture significantly shortens the design cycle and reduces verification effort and risk. This paper describes the key dimensions of extensibility within the processor architecture, the instruction set extension description language and the means of automatically extending the software environment from that description. It also describes two groups of benchmarks, EEMBC's Consumer and Telecommunications suites, that show 20 to 40 times acceleration of a broad set of algorithms through application-specific instruction set extension, relative to high performance RISC processors.

Programs naturally require a variety of memory-addressing modes. It isn't necessary to provide them in hardware, however, if a compiler can synthesize them from a few primitive modes. This not only simplifies the hardware, but also permits the compiler to use its understanding of the program to economize on the modes which it uses. We present some compilation techniques that allow the compiler to deal effectively with a single addressing mode in a target RISC processor. We also give measurements to show the benefits of such techniques, and to support our assertion that a single addressing mode is adequate for a general purpose processor, provided that mode incorporates both a pointer and an offset.