This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog style clock recovery circuits. The proposed circuit recovers output clock for every transition of input data and does not accumulate output jitter. It does not require any special exquisite techniques to detect the clock with appropriate phase. The phase shifts in recovered clock for input data skew are within ±40ps. The peak to-peak jitter is 49ps and RMS jitter is 4.5ps. The cycle-to-cycle jitter tolerance is ±33.3% UI. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for a pseudo random bit sequence of 2 -1 data at 2.56Gb/s. The acquisition time for the proposed circuit is fast enough to be used in burst-mode applications such as GPON.

The COSMOS symbolic fault simulator generates test sets for combinational and sequential MOS circuits represented at the switch level. All aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values are captured. To generate tests for a circuit, the program derives Boolean functions representing the behavior of the good and faulty circuits over a sequence of symbolic input patterns. It then determines a set of assignments to the input variables that will detect all faults. Symbolic simulation provides a natural framework for the user to supply an overall test strategy, letting the program determine the detailed conditions to detect a set of faults. Symbolic preprocessing of switch-level networks, combined with efficient Boolean manipulation makes this approach feasible.

The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator MOSSIM II.