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Wolfgang Rösner

dblp:41/2550 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › parasitic extraction
capacitance extraction		 0.011988
CAPCAL-a 3-D capacitance solver for support of CAD systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Electronic design automation › physical design
parasitic extraction		 0.011988
CAPCAL-a 3-D capacitance solver for support of CAD systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Integrated circuit design › interconnect
VLSI interconnect		 0.011988
CAPCAL-a 3-D capacitance solver for support of CAD systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988

Methods — techniques the papers use, named apart from their topics

multigrid solver · 0.0finite difference method · 0.0
YearPublicationVenuePosition
1988 CAPCAL-a 3-D capacitance solver for support of CAD systems
abstract
A program package is presented named CAPCAL that provides a method for calculation of the 3-D electric field distribution due to multilayer metallization of advanced VLSI (very large-scale integration) integrated circuits. The underlying physics and numerical modeling techniques used by CAPCAL are described. The finite-difference method together with a multigrid solver is used to permit easy program handling and full portability. Example capacitance calculations are presented for structures typical of the wiring of a memory cell. The influence of the line spacing and the permittivity of the passivation layer on the parasitic capacitances are also investigated. The codes developed have been tested on various computers down to the size of a microcomputer, and thus can be installed on every system currently in use for CAD.>
Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5