Silicon foundries are enabling fab-less chip design companies to meet market demand of highly integrated devices as mobile applications are flourishing in recent years. Foundries are also enabling other sectors of the semiconductor industry to provide high performance systems to meet the required bandwidth for mobile applications. Significant investments in the development of advanced technology nodes are made to ensure future demand are met. This makes Fab utilization of high importance. This paper discusses the importance of DFX (DFT, DFM, DFB, DFA) disciplines to accelerating technology bring up and enabling fast customer volume ramp up. We show how basic and advance DFT methodologies are used to design and test special structures to enable fast failure analysis identifying design and manufacturing constraints. We also discuss the role of DFX in failure analysis in improving the design and manufacturing rules.

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

This paper presents comprehensive defect analysis of digital CML circuits using detailed defect models at the device level. The circuits are based on Nortel's BiCMOS technology. A defect model macro has been used to analyze fourteen physical defects for each bipolar transistor and where all defects are being qualified as hard or soft. Defects are activated individually within CML gates which are exhaustively simulated and the responses compared to the response of equivalent gold circuits. Extracted data allow us to obtain both defect and fault coverages, and to generate statistics to assess the effectiveness of a given testing approach. For the CML gates studied, logical testing alone is not adequate as the coverage remained between 33% and 79%. By using combined testing the coverage was increased to 100%.

This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitors all gate output swings and flags all abnormal voltage excursions. These detectors cover classes of faults that cannot be tested by stuck-at testing methods only. Circuit simulations have shown that abnormal gate output excursions caused by the presence of a defect are common with CML. We also show that this technique works well below "at-speed" frequencies. Finally, variants of the built-in detectors with reduced area overhead are proposed.

Existing built-in self-test (BIST) diagnostic techniques assume the existence of a few bit errors in a test response sequence. This assumption is unrealistic since in a BIST environment a single defect can usually cause hundreds or thousands of errors in a test response sequence. Without making the above assumption, this paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices. Based on faulty signature information, our scheme guarantees correct identification of the scan flip-flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is able to identify failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is applicable to all voltage-detectable faults. It also applies naturally to multifrequency BIST. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also reported.

A new Built-In Self Test (BIST) technique suitable for high performance DSP datapaths is presented. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DP-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan based BIST technique is also presented. We show how DB-BIST can be used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.

Existing BIST diagnostic techniques assume the existence of a very few bit errors in a test response sequence. This assumption is unrealistic since in a practical BIST environment a single defect in a circuit can usually cause hundreds or thousands of errors in a test response sequence. This paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices, without making the above assumption. Based on faulty signature information our scheme guarantees correct identification of the scan flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is also capable of identifying the failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is able to diagnose all voltage-detectable faults. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also included.

A novel approach that links hardware structural testing to telecom system failure diagnostics software is presented. Issues related to accessing die hardware test features on the system are discussed and two access architectures are described. Linking the BIST to diagnostic software reduces the software complexity and at the same time increases the diagnostics accuracy. This technique has been implemented in several products.

A new fault insertion method to help debug diagnostic software of telecommunications systems is described. The method makes use of boundary scan to inject multiple and un-correlated faults in a telecom system carrying traffic. Both hardware and software implementation aspects are discussed. The new method allows the use of structural test as part of diagnostics software to locate faults.