Electronic System Level design has gained momentum in recent years and has found its way into industrial main stream. Using mobile phone platforms we identify historic and upcoming trends in system design. Virtual prototyping has become our main tool to attack the resulting design challenges. This methodology has direct implications on development flow and team setup. We explain basic concepts of transaction level modeling and highlight selected facets of our modeling practice. This is the introductory contribution to the tutorial System Level Design-An Industrial Perspective. A number of topics which are just touched in this paper are elaborated in dedicated focus contributions. The respective references are particularly emphasized by the triangle symbol.

This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs of competing performances at full simulator accuracy. Additionally, it identifies and evaluates the technological and structural constraints that prevent further performance improvement. The second method computes linear approximations to the feasible performance regions of circuits with a large number of performances. Both techniques allow a comparison of different circuit topologies with respect to their performance capabilities and contribute to hierarchical circuit sizing. The presented methods are validated by experimental results of Pareto-front computation and feasible performance region computation of operational amplifiers and hierarchical sizing of filters.

In this paper we present a method for the fast evaluation of circuit structures. It is part of a methodology for the structural synthesis of analog circuits which generates a large number of different circuit structures. Goal of the presented methods is to find circuit structures, which fit best the design goals. Based on implicit analog circuit specifications, as well as explicit performance specifications given by the designer, the presented method approximates the feasible region of parameters by a polytope. This polytopal approximation of the performance capabilities can be calculated and visualized or the feasibility of the specification can be tested by linear programming. The method has been validated on a set of operational amplifier structures

Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. In this paper, we present two deterministic approaches for PSE. One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. The other one computes discretizations of the Pareto front of competing performances. In addition, a motivation and application of PSE using a hierarchical design example is presented.

Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method.

We present a new technique to examine the trade-off regions of a circuit where its competing performances become "simultaneously optimal", i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and technological constraints, and an advanced multicriteria optimization formulation called normal-boundary intersection. We are able to efficiently calculate a well-balanced discretization of a Pareto surface, identify the active constraints, which prevent a further improvement, and even rank these constraints in terms of stringency. Experimental results demonstrate the efficacy and efficiency of the method and its potential for topology selection and analog synthesis.