A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented.

The authors describe a high-level functional analog simulator for hybrid logic/analog networks. it forms one level of an experimental multilevel simulation system which is currently under development. The functional simulator is described in detail, and the structure of the multilevel simulator is briefly outlined. It can be used as a stand-alone system but was developed specifically for coupling with other levels of simulation which also use time responses (or voltage waveforms). Since Boolean algebra cannot operate with time responses, a new algebra is developed. It eliminates the unknown state, the main obstacle in coupling analog simulation to logic simulation. Logic states are replaced by operations on time functions, in this case represented by piecewise linear segments. High-level analog operations are also possible. The simulator based on these ideas was used to solve several high-level analog problems. The examples presented demonstrate its application.>

It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC networks under certain conditions, the Elmore delay and the 50% unit step response delay are related by a constant which is largely independent of the element values and topology. An efficient method to obtain sensitivities of the delay with respect to any element in the network is presented.>

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation.>

The approximation of MOSFET nonlinearities by use of polynomial splines was investigated for reducing both circuit model development time and model simulation cost. After a brief tutorial on spline functions, it is shown how the number of independent variables for the MOSFET simulation models in digital circuits is reduced by their use. A tableau formulation for generating splines is presented along with a storage-reduction technique for polynomial spline coefficients. Mathematical programming problems for one-, two-, and three-dimensional splines are given that result in accurate monotonic splines using few segments. Two spline segments are shown to provide sufficient accuracy in the one-dimensional case, while 4*4 and 2*5*5 segments provide sufficient accuracy in the two- and three-dimensional cases, respectively.>

An algorithm for switch-level timing simulation of MOS logic networks is proposed. The event-driven simulator, WATSWITCH, partitions the circuit into subblocks which are solved by replacing each transistor by a special current-limited switch. Because of the choice of the switch model, time-domain responses are obtained without model evaluations during the simulation, without table lookup, and without time-domain integration. This is achieved by allowing only capacitors and piecewise-constant current sources to be the elements of the simulator. Because resistors are not allowed, the time responses are known to be piecewise-linear segments. As a consequence, neither numerical integration nor transistor model evaluation is needed during the simulation.>