Data centers provide good environments for distributed computing as they are easily accessible and may have low-latency communication between nodes [1] ; often, however, performance is limited by network bandwidth. These network bottlenecks drive the need for alternative communication resources to improve performance of large-scale applications. SmartNICs [2] – [4] have been introduced to perform the same tasks of standard NICs, but contain additional resources to allow for network function optimization with additional hardware. Adoption of SmartNICs continues to increase as a means to accelerate network functions and offload packet processing tasks away from CPU resources [5] – [13] .

PCI express (PCIe), the IO interconnect of choice in today's single host computing platform, is being enhanced to support features that include I/O virtualization and processor-coprocessor interconnect. Host-to-host communication, however, is regarded as beyond the scope of PCIe. As such, the model in today's multi-compute platforms is to utilize PCIe for communication between the host(s) and the IO subsystem while a dedicated clustering interconnect such as Infiniband or Ethernet is used for host-to-host communication. The Dolphin express solution (i.e. Dolphin's enhanced PCIe hardware and accompanying software) addresses the shortcoming of host-to-host communication in PCIe in a cost-effective manner. To the best of our knowledge, these products provide an industry first solution of using a PCIe-based switch fabric to seamlessly integrate both IO and clustering capabilities - thereby obviating the need for an additional clustering interconnect. As a first step towards providing a full-fledged clustering solution, we have enabled support for TCP/IP protocol over PCIe (IPoPCIe). Based on benchmarking results, IPoPCIe was able to achieve performance that was on par or better than that of a 10GigE NIC's. On a 2-node system connected using a switch, IPoPCIe shows an end-to-end application latency of ~14 mus and bandwidth of up to 1270 MB/S. Though the results are promising, the performance of IPoPCIe is greatly influenced by overheads associated with the TCP/IP protocol. Hence, work is ongoing on supporting a sockets direct interface that bypasses the TCP/IP stack. This would utilize the full potential of the underlying Dolphin Express hardware and lead to further reduction in latency, lower CPU utilization and increased bandwidth.

Dolphin express solution, comprising PCI express based hardware and accompanying software, is an industry first solution for seamlessly integrating IO and clustering capabilities onto an enhanced PCI express interconnect. This eliminates the need for two separate interconnects - one for IO and the other for clustering. Dolphin express components enable IO expansion in a single-host platform and provide clustering as well as IO expansion support in a multi-host platform. The hardware component of the Dolphin express solution consists of a (i) host adapter (ii) cluster switch (Hi) cluster/IO expansion switch. The software component provides the critical infrastructure for allowing legacy applications to run without the need for code rewrite or recompilation. The overall solution is such that the existence of an enhanced PCI express interconnect is completely transparent to legacy software - both on the PCI express expansion front as well as on the clustering front.

This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring a very deep pipeline and simultaneous multithreading. Performance of such a processor is highly dependent on the accuracy of its branch predictor and consequently a very large silicon area was devoted to branch prediction on EV8. The Alpha EV8 branch predictor relies on global history and features a total of 352 Kbits. The focus of this paper is on the different trade-offs performed to overcome various implementation constraints for the EV8 branch predictor. One such instance is the pipelining of the predictor on two cycles to facilitate the prediction of up to 16 branches per cycle from any two dynamically successive, 8 instruction fetch blocks. This resulted in the use of three fetch-block old compressed branch history information for accessing the predictor. Implementation constraints also restricted the composition of the index functions for the predictor and forced the usage of only single-ported memory cells. Nevertheless, we show that the Alpha EV8 branch predictor achieves prediction accuracy in the same range as the state-of-the-art academic global history branch predictors that do not consider implementation constraints in great detail.

Much emphasis is now being placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in applications. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for the speculative execution of sequential binaries without source recompilation. We present software support that enables the identification of threads from a sequential binary. The hardware includes a memory disambiguation mechanism that enables the detection of interthread memory dependence violations during speculative execution. This hardware is different from past proposals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermore, the architecture includes a simple and efficient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite effective in achieving high performance when running sequential binaries.

Chip-multiprocessors (CMP) are a promising approach for exploiting the increasing transistor count on a chip. To allow sequential applications to be executed on this architecture, current proposals incorporate hardware support to exploit speculative parallelism. However, these proposals either require re-compilation of the source program or use substantial hardware that tailors the architecture for speculative execution, thereby resulting in wasted resources when running parallel applications. In this paper, we present a CMP architecture that has hardware and software support for speculative execution of sequential binaries without the need for source re-compilation. The software support enables identification of threads from sequential binaries, while a modest amount of hardware allows register-level communication and enforces true inter-thread memory dependences. We evaluate this architecture and show that it is able to deliver high performance. 1 Introduction Current technology per...