This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.

As part of an industry wide effort the IEEE is in the process of standardizing the elements of test technology such that plug & play can be achieved when testing SoC designs. This standard under development is a language namely, Core Test Language (CTL), which is introduced in this paper. CTL describes all necessary information for test pattern reuse and the needs of test during system integration. CTL syntax and its link to STIL are explained with examples.

This paper presents a compression technique that reduces the test data volume while achieving high fault coverage within a Built-In Self-Test environment. The LFSR control data target only the RPR faults. The data are further reduced using a new code. Analysis of essential attributes of the control data is performed to assess their effect on the compression technique. The scheme was applied to several benchmark cores and indicated a superior effect than previously used compression techniques.