Productivity from day one on supercomputers that leverage new technologies requires significant preparation. An institution that procures a novel system architecture often lacks sufficient institutional knowledge and skills to prepare for it. Thus, the "Center of Excellence" (CoE) concept has emerged to prepare for systems such as Summit and Sierra, currently the top two systems in the Top 500. This paper documents CoE experiences that prepared a workload of diverse applications and math libraries for a heterogeneous system. We describe our approach to this preparation, including our management and execution strategies, and detail our experiences with and reasons for using different programming approaches. Our early science and performance results show that the project enabled significant early seismic science with up to a l4X throughput increase over Cori. In addition to our successes, we discuss our challenges and failures so others may benefit from our experience.

In most 3D work to date, people have looked at two situations: 1) a case in which power density is not a problem, and the parts of a processor and/or entire processors can be stacked atop each other, and 2) a case in which power density is limited, and storage is stacked atop processors. In this paper, we consider the case in which power density is a limitation, yet we stack processors atop processors. We also will discuss some of the physical limitations today that render many of the good ideas presented in other work impractical, and what would be required in the technology to make them feasible. In the high-performance regime, circuits are not designed to be “power efficient;” they're designed to be fast. In power-efficient design, the speed and power of a processor should be nearly proportional. In the high-performance regime, the frequency is (ever progressingly) sublinear in power. Thus, when the power density is constrained - as it is in high-performance machines, there may be opportunities to selectively exploit parallelism in workloads by running processor-on-processor systems at the same power, yet at much greater than half speed.

An extreme scale system is one that is one thousand times more capable than a current comparable system, with the same power and physical footprint. Intuitively, this means that the power consumption and physical footprint of a current departmental server should be enough to deliver petascale performance, and that a single, commodity chip should deliver terascale performance. In this panel, we will discuss the resulting challenges in energy/power efficiency, concurrency and locality, resiliency and programmability, and the research opportunities that may take us to extreme scale systems.

No abstract available.

Technology trends in recent years have led to the transition from chips containing one microprocessor core to chips containing multiple cores. This transition, first illustrated in server systems by the IBM Power4 microprocessor, is currently visible in designs ranging from dual-core desktop processors from different manufacturers, to nine cores in the recent IBM Cell microprocessor, up to over a hundred cores in various specialized systems (such as network processing or Java processing). The next step in the evolution of multi-core microprocessor architectures, which is already visible in some processor designs, consists of a more extensive integration at the chip-level, beyond the straight-forward aggregation of multiple cores on a chip. This enhanced integration is present at all levels, from the CMOS technology through processor architecture and microarchitecture, up to the on-chip system software.At the technology level, for example, the integration of embedded DRAM (eDRAM) on the same chip as the processor cores creates new design points that are different from those in SRAM-based designs. Similarly, three-dimensional integration offers the potential for becoming the successor to CMOS technology, in a similar manner as CMOS was the successor to bipolar technology, since there are similar tradeoffs in terms of power consumption, performance and density. At the processor architecture level, the integration of asymmetric cores (cores with the same instruction set architecture but different performance characteristics) and heterogeneous cores (cores with different functionality) is complemented with the integration of supporting functions that are increasing in their functionality (logic or processing cores for communications, direct memory access, data compression, security, power management, reconfigurable logic, etc.). In addition, new functionality expressed in terms of new instructions continues being architected into the processor cores. At the on-chip system software level, support for specialized features such as virtualization, dynamic execution environments, power management, is becoming part of the chip architecture. These innovations are enabling the evolution of microprocessors into "application-optimized systems" by leveraging modularity at all levels, in direct correlation to the levels where the innovations are taking place. As a result, new classes of applications and systems are expected to emerge, made possible by the significant gains achieved through the chip-level integration.While there are many reasons that support the trends in the evolution of chip-level integration for microprocessors, there are also many challenges in pursuing such objectives. The current trends make ever more important the need for identifying the emerging tradeoffs in chip-level architectures, the need to determine how those tradeoffs can be investigated and evaluated, and how proposed innovations can be incorporated at the chip level. The challenges that exist in this front can be illustrated with some recent examples, yet there are still many opportunities available in this emerging area which appears ready for further innovation. The resulting chip-level multi-core (parallel) microprocessors create new challenges/opportunities in terms of their programmability as well as in terms of the parallel algorithms that are best suited for their exploitation. Traditional techniques used in the development of parallel algorithms might no longer be sufficient to leverage the increasing heterogeneity in functionality becoming available in chip-level multiprocessors.

We describe a semi-custom design methodology for embedded processor cores that was prototyped through the development of a low power high performance DSP core. When compared to the standard ASIC design flow, this methodology enables significant improvement in the speed and power; such benefits are obtained without compromising the generality and flexibility that characterizes the ASIC-based design techniques. Our methodology achieves fast turn-around time in the process from RTL description to post-PD timing results, and exhibits stable convergence on timing; these characteristics enable the application of optimizations spanning multiple levels of the design hierarchy. Such optimizations proved to be much more effective than those that focus only on a single design stage.

This paper describes and evaluates three architectural methods for accomplishing data parallel computation in a programmable embedded system. Comparisons are made between the well-studied Very Long Instruction Word (VLIW) and Single Instruction Multiple Packed Data (SIMpD) paradigms; the less-common Single Instruction Multiple Disjoint Data (SIMdD) architecture is described and evaluated. A taxonomy is defined for data-level parallel architectures, and patterns of data access for parallel computation are studied, with measurements presented for over 40 essential telecommunication and media kernels. While some algorithms exhibit data-level parallelism suited to packed vector computation, it is shown that other kernels are most efficiently scheduled with more flexible vector models. This motivates exploration of non-traditional processor architectures for the embedded domain.

A low-power, high-performance, compiler-friendly DSP core has been under development in the IBM Communications Research & Development Center, as part of its eLite DSP project. This DSP incorporates instruction-level parallelism through the packing of multiple instructions in 64-bit long-instruction words, while data-level parallelism is realized through the use of SIMD techniques, such that SIMD operations can be applied to both dynamically composed vectors and packed vectors. Dynamic composition of vectors is made possible through the use of a vector pointer mechanism, which permits the addressing in a very flexible way of groups of four 16-bit elements in a large, multiport, scalar register file. This paper provides an overview of the architecture of this DSP core, with a focus on its SIMD features. We describe these features in some detail and discuss how they are used, with a block FIR filter and a radix-4 FFT taken as examples.

Many emerging applications, e.g. in the embedded and DSP space, are often characterized by their loopy nature where a substantial part of the execution time is spent within a few program phases. Loop buffering techniques have been proposed for capturing and processing these loops in small buffers to reduce the processor`s instruction fetch energy. However, these schemes are limited to straight-line or innermost loops and fail to adequately handle complex loops.In this paper, we propose a dynamic loop buffering mechanism that uses backwards branch control information to identify, capture and process complex loop structures. The DLB controller has been fully implemented in VHDL, synthesized and timed with the IBM Booledozer and Einstimer Synthesis tools, and analyzed for power with the Sequence PowerTheater tool. Our experiments show that the DLB approach, on average, results in a factor of 3 reduction in energy consumption compared to a traditional instruction memory design at an area overhead of about 9%.

We describe the results in validating the performance projections from a parameterized trace-driven simulation model of a speculative out-of-order superscalar processor which has been developed with the objective of acting as a microarchitecture exploration tool. Because of its objective, the model-called Turandot-has been designed to deliver much higher simulation speed than what is achieved from detailed (RTL) processor models. We summarize the validation methodology used, and present experimental data gathered in the calibration of one processor organization modeled with Turandot against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, Turandot is within 5% of the results reported by the reference model while exhibiting a speed-up factor of about 70.

We describe a representation o$instruction-level parallelism which does not requk checking dependencies at run-time, and which is suitable for processor implementations with vatying issue-width.In this approach, a prvgram is represented as a sequence oftreeinstructions, each containing multiple primitive operations.These tree-instnrctions are executable either in one or multiple cycles.do not require a speciJc processor organization.and are generated assuming an implementation capable of large instruction-level parallelism.During instruction cache reloading/accessing, treeinstructions am decomposed into sub-es which fit the actual resources available in an implementation.The resulting subtrees require a simple instruction-dispatch mechanism.as in the case of statically scheduled processors.The representation makes practical the use of the same parallelized code in implementations with different issue-width: simulation results indicate that the instruction-level parallelism achievable with this apptvach degrades less than 10% with respect to code compiled for each specific implementation.

The design of MAMACG, a software tool for automatically mapping an important class of matrix algorithms into mesh array computational graphs, is described. MAMACG is a concrete realization of the multimesh graph (MMG) method, implemented in Elk, a dialect of LISP with built-in X-graphics capabilities.>

The authors describe a processor for the execution of a class of matrix algorithms according to the multimesh graph (MMG) mapping method, which is suitable as the processing cell in an application-specific array. The processor uses the decoupled access-execute model of computation, so that it consists of two programmable units: a processing unit (PU) and an access unit (AU). The two programs synchronize their execution through queues. The instruction set includes single-instruction loops with no overhead, and block- loops with just one extra instruction. All storage modules are accessed as FIFO queues, without the need for addressing mechanisms. The efficiency of the resulting code is high: for a class of matrix algorithms frequently used in signal processing applications, about 90% of the instructions executed correspond to arithmetic operations.>

The authors describe the application of the multi-mesh graph (MMG) method to the mapping of large matrix algorithms onto class-specific local-access processor arrays. These arrays consist of cells with large local memory (i.e., memory size proportional to the size of the problems) and low cell bandwidth (much smaller than the cell computation rate). The results given indicate that the MMG method allows the analysis of such issues as allocation operations to cells, load balancing, scheduling, synchronization, and overhead in computations and data transfers. These aspects are illustrated by mapping the LU-decomposition algorithm onto a linear memory-linked array. Performance estimates indicate that mapping with the MMG method produces 94% utilization of cells in the target structure used. Therefore, the MMG is a suitable tool for mapping matrix algorithms onto pre-existing arrays.>