In recent years, spiking neural networks (SNNs) have progressively closed the performance gap with convolutional neural networks (CNNs), which are renowned for their success in complex artificial intelligence tasks. However, most existing SNN accelerators suffer from limited flexibility, lacking support for diverse convolutional topologies and struggling to deploy complex SNN models. To address these challenges, this article proposes a reconfigurable neuromorphic architecture, SConvNSys, tailored for accelerating spiking CNNs (SCNNs) across a wide range of applications. A fast, sparse detection technique, coupled with a dedicated sparse response unit, is introduced to effectively exploit the spatio-temporal sparsity inherent in spike-based computation. On this basis, a reconfigurable spiking convolution dataflow is designed to optimize computation across various SCNN structures. The proposed architecture supports multiple convolution types, including standard, transposed, dilated, and residual convolutions. Implemented on a field-programmable gate array (FPGA), SConvNSys achieves competitive results: for image classification, it attains recognition accuracies of 91.48% on CIFAR-10 and 68.54% on CIFAR-100, with a power consumption of just 1.8 W and a processing rate of 73 frames/s. In image segmentation tasks, it reaches 99.00% segmentation accuracy at 153 frames/s. For object detection, the proposed detection model achieves a mean intersection over union (MIoU) of 74.20%, with 0.11 giga operations (GOP) of convolutional computation, resulting in a throughput of 27.4 giga operations per second (GOPS) and an energy efficiency of 15.23 GOPS/W.

Currently, the performance of spiking neural networks (SNNs) under complicated tasks is gradually close to that of convolutional neural networks (CNNs). However, the existing neuromorphic computing hardware architectures (NCHAs) for accelerating SNNs lack effective sparse detection and cannot realize effective spatio-temporal parallel computing, resulting in high inference latency. In this paper, we propose an improved neuromorphic computing hardware architecture (called SiBrain) with high accuracy, low power and low latency, consisting of a sparse spatio-temporal parallel processing element (S$^{2}$TP-PE) array for spike convolution and pooling computation and a fully-connected (FC) Core for spike FC computation. In the novel S$^{2}$TP-PE array, a S$^{2}$TP computation unit is designed by using time-step and channel parallel computation techniques to reduce the latency caused by multiple time-steps of SNN, and a sparse detection and response unit is presented based on channel-cache and block-multiplex to achieve the spike detection, response, and reuse. Combining the above kernel components, the SiBrain is built and implemented on Virtex-7 FPGA with 200MHz. The experimental results show that the SiBrain can effectively support the deployment of SCNN models with different sizes, and the deployed large-scale Spiking Visual-Geometry-Group (VGG) model can achieve the recognition accuracies of 90.25% and 66.97% on CIFAR-10 and CIFAR-100 with the power consumption of 1.5 W and the energy efficiency of 83 GSOPs/W. Compared with existing FPGA-based SNN accelerators, SiBrain has a maximum increase in inference speed of nearly 11 times and a maximum decrease in energy consumption of nearly 34 times, respectively.

Spiking neural network (SNN) has attracted extensive attention in large-scale image processing tasks. To obtain higher computing efficiency, the development of hardware architecture suitable for SNN computing has become a hot research topic. However, the existing hardware of spike neurons still has high computational complexity and they do not perform well enough on complicated datasets, and the neuromorphic system cannot support SNNs with different convolutional topologies, resulting in low efficiency of the system. To address the above problems, an optimized leaky integrated-and-fire (LIF) neuron called EPC-LIF and a neuromorphic hardware acceleration system (ELIF-NHAS) are designed and implemented based on the field-programmable gate array (Xilinx Kintex-7). First, the classical LIF neuron is designed using the optimization method of extended prediction correction (EPC), which can reduce the computation complexity and hardware resources with a maximum frequency of 439.95 MHz. The ELIF-NHAS is constructed and optimized with parallel and pipeline techniques for effectively running SNNs, working with a maximum frequency of 135.6 MHz. Then, the genetic algorithm is applied to adjust the membrane threshold of neurons for further improving the accuracy of SNNs. Furthermore, the ELIF-NHAS can support different SNNs with multilayer perceptron and convolutional neural network topologies (called SCNN), including traditional, depth-separate, and residual convolutions. The accuracy of multilayer SCNNs can achieve 99.10%, 90.29%, and 82.15% on MNIST, Fashion-MNIST, and SVHN datasets, respectively; and the speed and energy consumption achieve 1.21 ms/image and 1.19 mJ/image. Compared with existing systems, the ELIF-NHAS is more suitable for the deployment and inference of SNNs with higher speed and lower consumption.

Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70%, 85.14% (LIF) and 97.81%, 83.16% (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively.