James M. Lebak

dblp:41/3698 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 37% High-performance computing · 34% Performance modeling and evaluation · 22%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel programming models
0.122005
Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005
Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing · IEEE Trans. Parallel Distributed Syst. 2000
High-performance computing › parallel numerical algorithms
parallel signal processing
0.112005
Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005
Performance modeling and evaluation › performance model construction
execution time modeling
0.012000
Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing · IEEE Trans. Parallel Distributed Syst. 2000
Parallel and multicore computing
parallel libraries
0.012000
Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing · IEEE Trans. Parallel Distributed Syst. 2000
Performance modeling and evaluation › performance prediction
parallel program performance prediction
0.012000
Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing · IEEE Trans. Parallel Distributed Syst. 2000
High-performance computing
space-time adaptive processing
0.012000
Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing · IEEE Trans. Parallel Distributed Syst. 2000
Embedded and real-time systems
real-time signal processing
0.012005
Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005

Methods — techniques the papers use, named apart from their topics

runtime optimization · 0.1offline mapping generation · 0.1adaptive optimization · 0.1
YearPublicationVenuePosition
2005 Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing
abstract
Real-time signal processing consumes the majority of the world's computing power. Increasingly, programmable parallel processors are used to address a wide variety of signal processing applications (e.g., scientific, video, wireless, medical, communication, encoding, radar, sonar, and imaging). In programmable systems, the major challenge is no longer hardware but software. Specifically, the key technical hurdle lies in allowing the user to write programs at high level, while still achieving performance and preserving the portability of the code across parallel computing hardware platforms. The Parallel Vector, Signal, and Image Processing Library (Parallel VSIPL++) addresses this hurdle by providing high-level C++ array constructs, a simple mechanism for mapping data and functions onto parallel hardware, and a community-defined portable interface. This paper presents an overview of the Parallel VSIPL++ standard as well as a deeper description of the technical foundations and expected performance of the library. Parallel VSIPL++ supports adaptive optimization at many levels. The C++ arrays are designed to support automatic hardware specialization by the compiler. The computation objects (e.g., fast Fourier transforms) are built with explicit setup and run stages to allow for runtime optimization. Parallel arrays and functions in Parallel VSIPL++ also support explicit setup and run stages, which are used to accelerate communication operations. The parallel mapping mechanism provides an external interface that allows optimal mappings to be generated offline and read into the system at runtime. Finally, the standard has been developed in collaboration with high performance embedded computing vendors and is compatible with their proprietary approaches to achieving performance.
James M. Lebak, Jeremy Kepner, Henry Hoffmann, Edward Rutledge
Proc. IEEE1
2001 VSIPL: an object-based open standard API for vector, signal, and image processing
abstract
VSIPL, the Vector, Signal, and Image Processing Library, is an open standard application programmer's interface (API) for signal and image processing. Defined by a consortium of industry, government, and academic representatives, VSIPL is gaining widespread acceptance as a de facto standard in the embedded signal processing world. The primary goal of the API is to increase the portability of vector signal processing, matrix signal processing, and image processing applications. We present an overview of the design, features, and availability of the VSIPL API.
Randall Janka, Randall Judd, James M. Lebak, Mark A. Richards, Dan Campbell
ICASSP3
2000 Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing
abstract
Space-time adaptive processing (STAP) refers to a class of methods for detecting targets using an array of sensors. Various STAP methods use similar operations on different data or in different orders. We have developed a portable, parallel library of subroutines for prototyping STAP methods. The subroutines work on the IBM SP2 and the Intel Paragon under three different operating systems and three different communication libraries, and can also be configured for other systems. We provide execution-time models for predicting the performance of each subroutine. Using the library routines, we created a parallel version of element-space pre-Doppler processing, three parallel versions of higher-order post-Doppler processing, and two versions of PRI-staggered post-Doppler processing. We implemented a fourth version of higher-order post-Doppler processing, the hybrid method, which uses a combination of fine-grain and coarse-grain parallelism to reduce execution time. The hybrid method can be used to improve performance when a large number of processors is available. Our execution time models generally predict the best method and predict execution times to within 10 percent or better for large test cases.
James M. Lebak, Adam W. Bojanczyk
IEEE Trans. Parallel Distributed Syst.1