Test generation for combinational circuits, an NP-complete problem, shows its worst-case behavior while trying to generate tests for redundant faults and failing after an exhaustive search. The performance of an automatic test generator can be significantly improved by identifying redundancy via simple techniques which do not involve a search. The authors present a technique to identify redundant faults. This technique works dynamically during test generation, but is not based on a search process. It relies on test-covering relations among faults, which allow identification of addition redundant faults after the test generator fails to generate a test for a target fault. This technique has been implemented in AT&T's Testpilot test generation system and has shown a reduction of up to 32% in the number of backtracks in test generation runs.>

The authors present a new cost function (GLOBAL) which is used to guide the decision process in test generation algorithms. By analyzing the global fanout structure of the circuit, GLOBAL guides the search for a test toward decisions that are least likely to result in conflict. The results obtained indicate that GLOBAL is a consistently superior guidance heuristic for test generation. Compared with previous cost functions, it provides greater fault coverage in approximately the same number of tests and usually in less CPU time. It appears to be more consistent and hence it can be reliably used on large circuits. GLOBAL identifies both lines whose justification is conflict free and lines whose justification is likely to lead to conflicts. Although its worst-case complexity is exponential in the number of stems, the analysis done by GLOBAL is performed only once, while its results are used at every decision step of an algorithm with a similar worst-case behavior. The results show that the time gained in test generation usually outweighs the time spent in preprocessing.>

The performance of an automatic test generator can be significantly improved by identifying redundancy by simple techniques which do not involve search. The authors present a technique for identifying redundant faults. This technique works dynamically during test generation but is not based on a search process. It exploits dominance and test-covering relations among faults, which allow identification of additional redundant faults after the test generator fails to generate a test for a target fault. This technique has been implemented in AT&T's LTG (LAMP2 test generation) system and has shown up to 32% reduction in the number of backtracks in test generation runs.>

The authors present the experience and strategy guiding the system-level computer-aided design verification (CADV) process used in the AT&T computer division. Specifically, they provide an overview of processes, results, and the strategy used to choose among modeling options, styles for the verification process, methods for test development, timing models, and techniques for analyzing results. CADV is now being used on ten active projects. The use of CADV has reduced the number of circuit board artmaster cycles required to produce a high-quality design for high-volume manufacture from an average of 3.5 to 4 cycles to an average of 2 cycles. >

The authors present the CAD tools used for system-level design verification (DV) in the AT&T computer division. They discuss features of the tools for building and preparing the model of the system, developing tests, simulation, static timing analysis, results analysis, and circuit comparison. While a good simulator is an essential component, many other tools are required. Although some of them provide only relatively minor capabilities, together they form an integrated set of tools that greatly simplify the designers' work and make possible successful completion of system-level DV projects.>

Stuck-at faults on primary inputs and fan-out branches are commonly used as target faults in test generation algorithms for combinational circuits. This correspondence shows that these faults may not constitute an adequate set of target faults. A procedure is presented for selecting a set of target faults with the property that the detection of all detectable faults from this set guarantees the detection of all detectable faults in the circuit.