Nowadays, people are getting more and more concern on their own fitness conditions and it has become a digital healthy lifestyle movement. A basic activity tracker has given many data on the user's movement to fulfill their daily goal of calories burned. An advance tracker can also measure heart rate with accurate activity intense level. However, consider if these fitness devices can be used for clinical diagnosis by adding an ECG, then it can be a daily health monitoring or a health assisted device by connecting it to the internet via a smartphone. To use an ECG as a wearable device, the electrode positions has to fulfill the clinical placement. A new biomedical electrodes placement is proposed in this paper to meet the practicality of a fitness lifestyle device but has a medical ECG result for continuous heart monitoring in a form of a necklace. The device has a single lead ECG analog front end that is connected to an ARM-Cortex M4 microcontroller. It uses a 4 GB memory card, rechargeable battery, and a Bluetooth Low Energy 4.0 to communicate with an Android 4.3 smartphone. The test results were taken from a 32-year-old male subject with normal heart condition. The signal acquired from the electrode placement at the backside of the neck shows Lead I waveform with 10% from the normal position amplitude value. The R-wave of every heartbeat can be seen for heart rate calculation. Therefore, it is able to do a daily heart monitoring with a lifestyle device.

Fault tolerance and energy consumption are two key aspects of future Network-on-Chips (NoCs). The utilization of deflection routing and Banyan networks for fault-tolerant and energy efficient router architectures was proposed recently. Compared to traditionally deployed crossbars, Banyan networks can reduce hardware costs and improve the energy efficiency of router architectures. However, they also cause substantial disadvantages in terms of fault tolerance, as they are internal blocking, single-path networks. In contrast, Benes networks have some considerable advantages if they are used for fault-tolerant NoCs, as they are rearrangeable non-blocking, multi-path networks. In this paper, we identify the problems of Banyan networks when it comes to fault tolerance. Further, we show that a router architecture, which is instead based on a Benes network, can solve all identified problems, if constructed carefully. Comparisons to existing fault-tolerant and deflection routing based NoCs are presented. The achieved results show, that compared to Banyan networks, Benes networks can improve the performance at almost no additional hardware costs.

Several ultrasound based localization systems consist of environmental anchor nodes, and mobile nodes, which estimate their own position by using a static infrastructure. For the location process, every anchor has to know its position. In most approaches, the location of all anchors has to be determined a priori manually. This procedure is time consuming and fault-prone. In this paper, we present Distribute & Erase and Explorer, two self-calibration methods for ultrasound based localization systems. The first uses a set of three pre-calibrated anchors to explore the whole localization system whereas the second refines the anchors' positions progressively. Both of our approaches require no additional hardware besides ultrasound receivers or transmitters, and radio transceivers, which have to be already available for the WSN based localization system.

Localization of objects within space is a common problem in WSN research. Besides the location estimation itself, wireless communication is a central aspect within such systems. We present the novel HashSlot method for assured and collision-free transmission of radio packets from multiple sources to a common destination within a constant and predictable time. Due to self-organization, our approach needs no prior active coordination between sensor nodes and offers various techniques like selectable quality of service levels to dynamically limit the number of returned information during runtime. Thereby, precision and speed of the localization process can be adjusted, fault tolerance can be achieved and energy consumption will be reduced. This paper describes theory and application of the HashSlot method within a real WSN based localization system.

The real-world implementation of a just theoretically elaborated idea is sometimes cumbersome, often a couple of obstacles have to be overcome. That's likewise in the area of wireless sensor networks (WSN), but complicated by some further restrictions, e.g. little memory or low power consumption. One well-known and often required application within WSN is the geographical localization of several sensor nodes. That's why this paper deals with some problems arising during the development of a WSN using the time difference of arrival (TDoA) of ultrasound and radio signals for positioning. Its focus is on handling of microcontroller difficulties like little memory, low computational power or low energy consumption as well as hardware driven failures like inaccurate measurements or node failures.

In their 1991 paper "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding", Parhi and Messerschmidt stated a perfect-rate property on unfolded data-flow graphs (DFGs). This is disproven by a simple counter example.

In this paper we address the problem of state encoding for synchronous finite state machines. The primary goal is the reduction of switching activity in the state register. At the beginning the state transition graph is transformed into an undirected graph where the edges are labeled with the state transition probabilities. Next a maximum spanning tree of the undirected graph is constructed and we formulate the state encoding problem as an embedding of the spanning tree into a Boolean hypercube of unknown dimension. At this point a modification of Prim's maximum spanning tree algorithm is presented to limit the dimension of the hypercube for area constraints. Then we propose a polynomial time embedding heuristic, which removes the restriction of previous works, where the number of state bits used for encoding of a k-state FSM was generally limited to [log/sub 2/ k]. Next a more sophisticated embedding algorithm is presented, which takes into account the state transition probabilities not covered by the spanning tree. The resulting encodings of both algorithms often exhibit a lower switching activity and power dissipation in comparison with a known heuristic for low power state encoding.

Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. CPU time also remains small for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN equivalence class. We show how this representative can be computed efficiently and how it can be used for matching a boolcan function against a set of library functions.

In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation.We present a normalization algorithm which extracts the largest nodes of the given netlist.Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes.Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) d an uncorrelated signal probabilities.

In this paper we present a new approach to the synthesis of combinational circuits and the mapping of standard gates like NAND, NOR, AOI and OAI with arbitrary number of inputs. Our method is based on the provable optimal synthesis of the fan-out-free regions of a circuit, represented as normal AND-OR-trees. Normal AND-OR-trees enable TROY to rebalance the regions with respect to delay without loosing area and lead to a much larger search space than that used by tree matching. Fast heuristics derived from the optimal approach yield significantly faster results than SIS on many standard benchmark circuits.

This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mapping based methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for duplication of logic and for AT-tradeoffs are developed and applied to LUT-FPGAs.

The following optimization problem is considered. Assume that each gate of a given circuit can be realized by one of several implementations which have different physical properties. Given this assumption, realizations of the circuit with optimal area delay tradeoff are sought. The formal model used is a discrete version of the transistor sizing problem on one hand and a special case of the library mapping problem on the other hand. It is independent of technology and applicable to even very restrictive design styles, as, for example, gate arrays or sea of gates. Since sizing of general combinational circuits is NP-complete, it is proposed to use heuristics on the base of optimal solutions for subcircuits. With this in mind, an efficient dynamic programming algorithm for minimizing the delay of a fanout-free circuit (tree) under an area constraint is presented.>

We present an algebraic approach to hierarchical design of integrated circuits. This approach is based on a of nets which includes topological as well as behavioural aspects of integrated circuits. We have developed a hierarchical design system called CADIC which is build around this calculus in much the same way as e.g. Algol is build around numerics. An example for the design of a family of fast adders will demonstrate the power of this calculus. Finally we will give a summary outline on the structure of procedures which automatically transform the design into lower design levels.