Modular exponentiation with large modulus and exponent has been widely used in public key cryptosystems. Montgomery's modular multiplication algorithm is normally used since no trial division is necessary and the critical path is reduced by using carry-save addition (CSA). In this paper, the Montgomery multiplication is greatly optimized and architectures are proposed to perform the Least-Significant-Bit (LSB) first and the Most-Significant-Bit (MSB) first algorithms. The architecture here presented has the following distinctive characteristics: 1) Use of digit-serial approach for Montgomery multiplication. 2) Conversion of the CSA representation of intermediate multiplication using carry-skip addition which reduces the critical path with a small area-speed penalty. 3) Precompute quotient value in Montgomery iteration in order to speed up operation frequency. In this work, implementation results in Xilinx Virtex 5 and Virtex 2 are reported. Experimental results show that the proposed modular exponentiation and modular multiplication design obtains the best delay performance compared with previous published works and outperforms them in terms of area-time complexity.

This paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. The algorithm is suitable for fixed-point operands and divides in a radix r = 2k, producing k bits at each iteration. The proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one optimized for configurable logic. Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. The dividers were also compared against Xilinx CoreGenerator circuits clearly outperforming latency and area.

A generalized version of the plus-minus algorithm is used for implementing dividers over GF(p/sup n/). Generic dividers have been synthesized in the general case of GF(p/sup n/) and in the particular cases of GF(2/sup n/) and GF(p). The theoretical costs are O(logN) being N the number of field elements, and the theoretical computation times are O(logN) in the case of dividers over GF(p/sup n/) and GF(2/sup n/), and O((logN)/sup 2/) in the case of dividers over GF(p). Finally, the results of FPGA implementations are reported, and a comparison is made between dividers over GF(p), GF(2/sup n/) and GF(p/sup n/).

Algebraic methods for designing multiple-valued I2L circuits are presented. A new operation, namely the truncated difference, is introduced and proved to be an efficient tool for both analyzing and synthesizing circuits.

The total and local unateness of discrete and of switching functions are studied from a theoretical point of view. One shows that the local unateness leads to the concept of hazard-free transition for a discrete function. Unate covers for discrete functions are defined: they are either the smallest unate functions larger than a discrete function, or the largest unate functions smaller than a discrete function. These concepts play a key role in hazard-free design of multiple-valued networks. Three-level types of multiple-valued networks using MIN and MAX gates are presented. These networks improve, from a hazard point of view the well known two-level networks presented by Eichel-berger in the frame of switching theory.