Demo Data from EDBT 2026 / reviewers in the wild / expert
J. Kella
dblp:41/425
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1979
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 1979 | Detection of Hazards in Combinational Switching Circuits · IEEE Trans. Computers 1979 |
Electronic design automation › hardware verification and test
hazard detection |
0.0 | 1 | 1979 | Detection of Hazards in Combinational Switching Circuits · IEEE Trans. Computers 1979 |
Methods — techniques the papers use, named apart from their topics
spike superposition analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1979 | Detection of Hazards in Combinational Switching CircuitsabstractThis correspondence investigates a systematic binary technique for detecting static and dynamic hazards in combinational networks. The technique is based on deriving the conditions for the occurrence of spikes and considering a hazard as a superposition of spikes. Y. Zisapel, M. Krieger, J. Kella |
IEEE Trans. Computers | 3 |